-
Notifications
You must be signed in to change notification settings - Fork 1
/
sync_ram_tb.v
76 lines (54 loc) · 1.2 KB
/
sync_ram_tb.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
`define ADDR_WIDTH 4
`define DEPTH 16
`define DATA_WIDTH 8
module sync_ram_tb ();
reg clk,rst,we;
reg [`ADDR_WIDTH-1:0] addr;
wire [`DATA_WIDTH-1:0] data;
reg [`DATA_WIDTH-1:0] tempdata;
sync_ram_16X8 dut (clk,rst,we,addr,data);
assign data = (we)? tempdata:8'hzz;
task reset(); //reset task
begin
@(negedge clk) rst=1'b1;
@(negedge clk) rst=1'b0;
end
endtask
task clock(); //clocking task
begin
clk=1'b1;
forever #10 clk=~clk;
end
endtask
task write(
input [`DATA_WIDTH-1:0] wdata,
input [`ADDR_WIDTH-1:0] waddr); //write task
begin
@(negedge clk)
we=1'b1;
addr= waddr;
tempdata=wdata;
end
endtask
task read(input [`ADDR_WIDTH-1:0] raddr ); //read task
begin
@(negedge clk)begin
we=1'b0;
addr=raddr;
end
end
endtask
initial begin
clock();
end
initial begin
reset();
repeat(4) @(negedge clk) write({$random},{$random}); //random read write op
repeat(2) @(negedge clk) read({$random});
repeat(4) @(negedge clk) write({$random},{$random});
repeat(2) @(negedge clk) read({$random});
reset();
repeat(4) @(negedge clk) write({$random},{$random});
#200 $finish;
end
endmodule