video_stitcher_tb.vcd

$date
	Fri Apr 30 19:54:21 2021
$end
$version
	Icarus Verilog
$end
$timescale
	1ns
$end
$scope module video_stitcher_tb $end
$var wire 1 ! rw_2 $end
$var wire 1 " rw_1 $end
$var wire 1 # pause $end
$var wire 1 $ fill_now $end
$var wire 1 % data_valid $end
$var wire 1 & camera_enable $end
$var wire 8 ' camera_data [7:0] $end
$var wire 1 ( RWM_2_valid $end
$var wire 1 ) RWM_2_enable $end
$var wire 1 * RWM_2_done $end
$var wire 8 + RWM_2_data [7:0] $end
$var wire 1 , RWM_1_valid $end
$var wire 1 - RWM_1_enable $end
$var wire 1 . RWM_1_done $end
$var wire 8 / RWM_1_data [7:0] $end
$var wire 1 0 GS_valid $end
$var wire 1 1 GS_enable $end
$var wire 1 2 GS_done $end
$var wire 8 3 GS_data [7:0] $end
$var wire 16 4 Dout [15:0] $end
$var reg 1 5 clear $end
$var reg 1 6 clk $end
$var reg 1 7 rst_n $end
$var reg 1 8 start $end
$scope module FILTER $end
$var wire 1 6 clk $end
$var wire 1 7 rst $end
$var wire 1 $ fill_now $end
$var wire 1 ( data_valid $end
$var wire 16 9 Dout [15:0] $end
$var wire 8 : Din [7:0] $end
$var reg 2 ; NS [1:0] $end
$var reg 2 < PS [1:0] $end
$var reg 16 = result [15:0] $end
$var reg 16 > result0 [15:0] $end
$var reg 16 ? result1 [15:0] $end
$var reg 16 @ result2 [15:0] $end
$var reg 16 A result3 [15:0] $end
$var integer 32 B count [31:0] $end
$var integer 32 C i [31:0] $end
$var integer 32 D j [31:0] $end
$var integer 32 E k [31:0] $end
$upscope $end
$scope module GS $end
$var wire 1 6 clk $end
$var wire 1 7 rst_n $end
$var wire 1 # pause $end
$var wire 1 , RWM_valid $end
$var wire 1 0 GS_valid $end
$var wire 1 1 GS_enable $end
$var wire 8 F Dout [7:0] $end
$var wire 8 G Din [7:0] $end
$var reg 2 H CS [1:0] $end
$var reg 1 2 GS_done $end
$var reg 2 I NS [1:0] $end
$var reg 8 J blue [7:0] $end
$var reg 8 K green [7:0] $end
$var reg 8 L red [7:0] $end
$var reg 8 M result [7:0] $end
$var integer 32 N c [31:0] $end
$var integer 32 O d [31:0] $end
$upscope $end
$scope module Memory_1 $end
$var wire 1 5 clear $end
$var wire 1 6 clk $end
$var wire 1 # pause $end
$var wire 1 7 rst_n $end
$var wire 1 " rw $end
$var wire 8 P data_out [7:0] $end
$var wire 8 Q data_in [7:0] $end
$var wire 1 , RWM_valid $end
$var wire 1 - RWM_enable $end
$var reg 3 R CS [2:0] $end
$var reg 3 S NS [2:0] $end
$var reg 1 . RWM_done $end
$var integer 32 T i [31:0] $end
$var integer 32 U j [31:0] $end
$upscope $end
$scope module Memory_2 $end
$var wire 1 0 GS_valid $end
$var wire 1 5 clear $end
$var wire 1 6 clk $end
$var wire 8 V data_in [7:0] $end
$var wire 1 7 rst_n $end
$var wire 1 ! rw $end
$var wire 8 W data_out [7:0] $end
$var wire 1 ( RWM_valid $end
$var wire 1 ) RWM_enable $end
$var reg 3 X CS [2:0] $end
$var reg 3 Y NS [2:0] $end
$var reg 1 * RWM_done $end
$var integer 32 Z i [31:0] $end
$var integer 32 [ j [31:0] $end
$upscope $end
$scope module control $end
$var wire 1 2 GS_done $end
$var wire 1 . RWM_1_done $end
$var wire 1 * RWM_2_done $end
$var wire 1 6 clk $end
$var wire 1 7 rst_n $end
$var wire 1 8 start $end
$var wire 1 ! rw_2 $end
$var wire 1 " rw_1 $end
$var wire 1 & camera_enable $end
$var wire 1 ) RWM_2_enable $end
$var wire 1 - RWM_1_enable $end
$var wire 1 1 GS_enable $end
$var reg 3 \ CS [2:0] $end
$var reg 3 ] NS [2:0] $end
$upscope $end
$scope module interface $end
$var wire 1 & camera_en $end
$var wire 1 6 clk $end
$var reg 8 ^ data_out [7:0] $end
$var reg 1 % data_valid $end
$var integer 32 _ ptr [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
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$end
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#13
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#28
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#33
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16
#49
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16
#51
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#53
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#55
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16
#57
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16
#59
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16
#61
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#62
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#63
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#64
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#65
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#67
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#69
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#95
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#109
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#117
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#119
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#133
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#135
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#137
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#141
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#143
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#145
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#159
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#183
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