From ef305f9c8e9972aa938140e0c638c92d6c366ab9 Mon Sep 17 00:00:00 2001
From: cailue <cailue@bupt.edu.cn>
Date: Mon, 7 Oct 2024 01:23:06 +0800
Subject: [PATCH] chore: remove redundant println in tests

Signed-off-by: cailue <cailue@bupt.edu.cn>
---
 src/sim.rs | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/src/sim.rs b/src/sim.rs
index d493298..35ce02e 100644
--- a/src/sim.rs
+++ b/src/sim.rs
@@ -293,7 +293,6 @@ mod tests {
 
         aig.add_output(x1);
 
-        println!("{}", aig.to_string());
         let pattern = vec![
             vec![true, true], // step 0 reset to initial state
             vec![false, true],
@@ -337,12 +336,6 @@ mod tests {
             vec![true, true, true, true, true],
         ];
 
-        println!(
-            "LUT vars: {}\n LUT size: {}",
-            truth.num_vars(),
-            truth.num_bits()
-        );
-
         let expected: Vec<Vec<_>> = vec![0, 0, 0, 1, 1]
             .into_iter()
             .map(|b| vec![b == 1])