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Dask.h
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Dask.h
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#ifndef _DASK_H
#define _DASK_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* DASK Data Types
*/
typedef unsigned char U8;
typedef short I16;
typedef unsigned short U16;
typedef long I32;
typedef unsigned long U32;
typedef float F32;
typedef double F64;
/*
* ADLink PCI Card Type
*/
#define PCI_6208V 1
#define PCI_6208A 2
#define PCI_6308V 3
#define PCI_6308A 4
#define PCI_7200 5
#define PCI_7230 6
#define PCI_7233 7
#define PCI_7234 8
#define PCI_7248 9
#define PCI_7249 10
#define PCI_7250 11
#define PCI_7252 12
#define PCI_7296 13
#define PCI_7300A_RevA 14
#define PCI_7300A_RevB 15
#define PCI_7432 16
#define PCI_7433 17
#define PCI_7434 18
#define PCI_8554 19
#define PCI_9111DG 20
#define PCI_9111HR 21
#define PCI_9112 22
#define PCI_9113 23
#define PCI_9114DG 24
#define PCI_9114HG 25
#define PCI_9118DG 26
#define PCI_9118HG 27
#define PCI_9118HR 28
#define PCI_9810 29
#define PCI_9812 30
#define PCI_7396 31
#define PCI_9116 32
#define PCI_7256 33
#define PCI_7258 34
#define PCI_7260 35
#define PCI_7452 36
#define PCI_7442 37
#define PCI_7443 38
#define PCI_7444 39
#define PCI_9221 40
#define PCI_9524 41
#define PCI_6202 42
#define PCI_9222 43
#define PCI_9223 44
#define PCI_7433C 45
#define PCI_7434C 46
#define PCI_922A 47
#define PCI_7350 48
#define PCI_7360 49
#define MAX_CARD 32
/*
* Error Number
*/
#define NoError 0
#define ErrorUnknownCardType -1
#define ErrorInvalidCardNumber -2
#define ErrorTooManyCardRegistered -3
#define ErrorCardNotRegistered -4
#define ErrorFuncNotSupport -5
#define ErrorInvalidIoChannel -6
#define ErrorInvalidAdRange -7
#define ErrorContIoNotAllowed -8
#define ErrorDiffRangeNotSupport -9
#define ErrorLastChannelNotZero -10
#define ErrorChannelNotDescending -11
#define ErrorChannelNotAscending -12
#define ErrorOpenDriverFailed -13
#define ErrorOpenEventFailed -14
#define ErrorTransferCountTooLarge -15
#define ErrorNotDoubleBufferMode -16
#define ErrorInvalidSampleRate -17
#define ErrorInvalidCounterMode -18
#define ErrorInvalidCounter -19
#define ErrorInvalidCounterState -20
#define ErrorInvalidBinBcdParam -21
#define ErrorBadCardType -22
#define ErrorInvalidDaRefVoltage -23
#define ErrorAdTimeOut -24
#define ErrorNoAsyncAI -25
#define ErrorNoAsyncAO -26
#define ErrorNoAsyncDI -27
#define ErrorNoAsyncDO -28
#define ErrorNotInputPort -29
#define ErrorNotOutputPort -30
#define ErrorInvalidDioPort -31
#define ErrorInvalidDioLine -32
#define ErrorContIoActive -33
#define ErrorDblBufModeNotAllowed -34
#define ErrorConfigFailed -35
#define ErrorInvalidPortDirection -36
#define ErrorBeginThreadError -37
#define ErrorInvalidPortWidth -38
#define ErrorInvalidCtrSource -39
#define ErrorOpenFile -40
#define ErrorAllocateMemory -41
#define ErrorDaVoltageOutOfRange -42
#define ErrorDaExtRefNotAllowed -43
#define ErrorDIODataWidthError -44
#define ErrorTaskCodeError -45
#define ErrortriggercountError -46
#define ErrorInvalidTriggerMode -47
#define ErrorInvalidTriggerType -48
#define ErrorInvalidCounterValue -50
#define ErrorInvalidEventHandle -60
#define ErrorNoMessageAvailable -61
#define ErrorEventMessgaeNotAdded -62
#define ErrorCalibrationTimeOut -63
#define ErrorUndefinedParameter -64
#define ErrorInvalidBufferID -65
#define ErrorInvalidSampledClock -66
#define ErrorInvalidOperationMode -67
/*Error number for driver API*/
#define ErrorConfigIoctl -201
#define ErrorAsyncSetIoctl -202
#define ErrorDBSetIoctl -203
#define ErrorDBHalfReadyIoctl -204
#define ErrorContOPIoctl -205
#define ErrorContStatusIoctl -206
#define ErrorPIOIoctl -207
#define ErrorDIntSetIoctl -208
#define ErrorWaitEvtIoctl -209
#define ErrorOpenEvtIoctl -210
#define ErrorCOSIntSetIoctl -211
#define ErrorMemMapIoctl -212
#define ErrorMemUMapSetIoctl -213
#define ErrorCTRIoctl -214
#define ErrorGetResIoctl -215
#define ErrorCalIoctl -216
#define ErrorPMIntSetIoctl -217
/*
* AD Range
*/
#define AD_B_10_V 1
#define AD_B_5_V 2
#define AD_B_2_5_V 3
#define AD_B_1_25_V 4
#define AD_B_0_625_V 5
#define AD_B_0_3125_V 6
#define AD_B_0_5_V 7
#define AD_B_0_05_V 8
#define AD_B_0_005_V 9
#define AD_B_1_V 10
#define AD_B_0_1_V 11
#define AD_B_0_01_V 12
#define AD_B_0_001_V 13
#define AD_U_20_V 14
#define AD_U_10_V 15
#define AD_U_5_V 16
#define AD_U_2_5_V 17
#define AD_U_1_25_V 18
#define AD_U_1_V 19
#define AD_U_0_1_V 20
#define AD_U_0_01_V 21
#define AD_U_0_001_V 22
#define AD_B_2_V 23
#define AD_B_0_25_V 24
#define AD_B_0_2_V 25
#define AD_U_4_V 26
#define AD_U_2_V 27
#define AD_U_0_5_V 28
#define AD_U_0_4_V 29
/*------------------*/
/* Common Constants */
/*------------------*/
/* T or F*/
#define TRUE 1
#define FALSE 0
/*Synchronous Mode*/
#define SYNCH_OP 1
#define ASYNCH_OP 2
/*AO Terminate Mode*/
#define DA_TerminateImmediate 0
/*DIO Port Direction*/
#define INPUT_PORT 1
#define OUTPUT_PORT 2
/*DIO Line Direction*/
#define INPUT_LINE 1
#define OUTPUT_LINE 2
/*Clock Mode*/
#define TRIG_SOFTWARE 0
#define TRIG_INT_PACER 1
#define TRIG_EXT_STROBE 2
#define TRIG_HANDSHAKE 3
#define TRIG_CLK_10MHZ 4
#define TRIG_CLK_20MHZ 5
#define TRIG_DO_CLK_TIMER_ACK 6
#define TRIG_DO_CLK_10M_ACK 7
#define TRIG_DO_CLK_20M_ACK 8
/*Virtual Sampling Rate for using external clock as the clock source*/
#define CLKSRC_EXT_SampRate 10000
/*Register by slot*/
#define RegBySlot 0x8000
/*PCI info*/
#define PCILocInfo(bus, dev, fun) \
RegBySlot|((bus&0xffff)<<8)|((dev&0x1f)<<3)|(fun&0x7)
/*DIO & AFI Voltage Level*/
#define VoltLevel_3R3 0
#define VoltLevel_2R5 1
#define VoltLevel_1R8 2
/*---------------------------------------------*/
/* Constants for PCI-6208A/PCI-6308A/PCI-6308V */
/*---------------------------------------------*/
/*Output Mode*/
#define P6208_CURRENT_0_20MA 0
#define P6208_CURRENT_4_20MA 3
#define P6208_CURRENT_5_25MA 1
#define P6308_CURRENT_0_20MA 0
#define P6308_CURRENT_4_20MA 3
#define P6308_CURRENT_5_25MA 1
/*AO Setting*/
#define P6308V_AO_CH0_3 0
#define P6308V_AO_CH4_7 1
#define P6308V_AO_UNIPOLAR 0
#define P6308V_AO_BIPOLAR 1
/*------------------------*/
/* Constants for PCI-7200 */
/*------------------------*/
/*InputMode*/
#define DI_WAITING 0x02
#define DI_NOWAITING 0x00
#define DI_TRIG_RISING 0x04
#define DI_TRIG_FALLING 0x00
#define IREQ_RISING 0x08
#define IREQ_FALLING 0x00
/*Output Mode*/
#define OREQ_ENABLE 0x10
#define OREQ_DISABLE 0x00
#define OTRIG_HIGH 0x20
#define OTRIG_LOW 0x00
/*----------------------------------*/
/* Constants for PCI-7248/7296/7396 */
/*----------------------------------*/
/*Channel & Port*/
#define Channel_P1A 0
#define Channel_P1B 1
#define Channel_P1C 2
#define Channel_P1CL 3
#define Channel_P1CH 4
#define Channel_P1AE 10
#define Channel_P1BE 11
#define Channel_P1CE 12
#define Channel_P2A 5
#define Channel_P2B 6
#define Channel_P2C 7
#define Channel_P2CL 8
#define Channel_P2CH 9
#define Channel_P2AE 15
#define Channel_P2BE 16
#define Channel_P2CE 17
#define Channel_P3A 10
#define Channel_P3B 11
#define Channel_P3C 12
#define Channel_P3CL 13
#define Channel_P3CH 14
#define Channel_P4A 15
#define Channel_P4B 16
#define Channel_P4C 17
#define Channel_P4CL 18
#define Channel_P4CH 19
#define Channel_P5A 20
#define Channel_P5B 21
#define Channel_P5C 22
#define Channel_P5CL 23
#define Channel_P5CH 24
#define Channel_P6A 25
#define Channel_P6B 26
#define Channel_P6C 27
#define Channel_P6CL 28
#define Channel_P6CH 29
/*the following are used for PCI7396*/
#define Channel_P1 30
#define Channel_P2 31
#define Channel_P3 32
#define Channel_P4 33
#define Channel_P1E 34
#define Channel_P2E 35
#define Channel_P3E 36
#define Channel_P4E 37
/*----------------------------------*/
/* Constants for PCI-7442/7443/7444 */
/*----------------------------------*/
/*P7442*/
#define P7442_CH0 0
#define P7442_CH1 1
#define P7442_TTL0 2
#define P7442_TTL1 3
/*P7443*/
#define P7443_CH0 0
#define P7443_CH1 1
#define P7443_CH2 2
#define P7443_CH3 3
#define P7443_TTL0 4
#define P7443_TTL1 5
/*P7444*/
#define P7444_CH0 0
#define P7444_CH1 1
#define P7444_CH2 2
#define P7444_CH3 3
#define P7444_TTL0 4
#define P7444_TTL1 5
/*COS Counter OP*/
#define COS_COUNTER_RESET 0
#define COS_COUNTER_SETUP 1
#define COS_COUNTER_START 2
#define COS_COUNTER_STOP 3
#define COS_COUNTER_READ 4
/*
* EMG shdn ctrl code
*/
#define EMGSHDN_OFF 0
#define EMGSHDN_ON 1
#define EMGSHDN_RECOVERY 2
/*
* Hot Reset Hold ctrl code
*/
#define HRH_OFF 0
#define HRH_ON 1
/*-------------------------*/
/* Constants for PCI-7300A */
/*-------------------------*/
/*Wait Status*/
#define P7300_WAIT_NO 0
#define P7300_WAIT_TRG 1
#define P7300_WAIT_FIFO 2
#define P7300_WAIT_BOTH 3
/*Terminator control*/
#define P7300_TERM_OFF 0
#define P7300_TERM_ON 1
/*DI control signals polarity for PCI-7300A Rev. B*/
#define P7300_DIREQ_POS 0x00000000L
#define P7300_DIREQ_NEG 0x00000001L
#define P7300_DIACK_POS 0x00000000L
#define P7300_DIACK_NEG 0x00000002L
#define P7300_DITRIG_POS 0x00000000L
#define P7300_DITRIG_NEG 0x00000004L
/*DO control signals polarity for PCI-7300A Rev. B*/
#define P7300_DOREQ_POS 0x00000000L
#define P7300_DOREQ_NEG 0x00000008L
#define P7300_DOACK_POS 0x00000000L
#define P7300_DOACK_NEG 0x00000010L
#define P7300_DOTRIG_POS 0x00000000L
#define P7300_DOTRIG_NEG 0x00000020L
/*DO Disable mode in DO_AsyncClear*/
#define P7300_DODisableDOEnabled 0
#define P7300_DONotDisableDOEnabled 1
/*----------------------------------------------*/
/* Constants for PCI-7432/7433/7434/7433C/7434C */
/*----------------------------------------------*/
#define PORT_DI_LOW 0
#define PORT_DI_HIGH 1
#define PORT_DO_LOW 0
#define PORT_DO_HIGH 1
#define P7432R_DO_LED 1
#define P7433R_DO_LED 0
#define P7434R_DO_LED 2
#define P7432R_DI_SLOT 1
#define P7433R_DI_SLOT 2
#define P7434R_DI_SLOT 0
/*----------------------------------------------------------------------------*/
/* Dual-Interrupt Source control for PCI-7248/96 & 7432/33 & 7230 & 8554 & */
/* 7396 & 7256 & 7260 & 7442/43/44 & 7433C */
/*----------------------------------------------------------------------------*/
#define INT1_NC -2
#define INT1_DISABLE -1
#define INT1_COS 0
#define INT1_FP1C0 1
#define INT1_RP1C0_FP1C3 2
#define INT1_EVENT_COUNTER 3
#define INT1_EXT_SIGNAL 1
#define INT1_COUT12 1
#define INT1_CH0 1
#define INT1_COS0 1
#define INT1_COS1 2
#define INT1_COS2 4
#define INT1_COS3 8
#define INT2_NC -2
#define INT2_DISABLE -1
#define INT2_COS 0
#define INT2_FP2C0 1
#define INT2_RP2C0_FP2C3 2
#define INT2_TIMER_COUNTER 3
#define INT2_EXT_SIGNAL 1
#define INT2_CH1 2
#define INT2_WDT 4
#define ManualResetIEvt 0x4000
#define WDT_OVRFLOW_SAFETYOUT 0x8000
/*------------------------*/
/* Constants for PCI-8554 */
/*------------------------*/
/*Clock Source of Cunter N*/
#define ECKN 0
#define COUTN_1 1
#define CK1 2
#define COUT10 3
/*Clock Source of CK1*/
#define CK1_C8M 0
#define CK1_COUT11 1
/*Debounce Clock*/
#define DBCLK_COUT11 0
#define DBCLK_2MHZ 1
/*------------------------*/
/* Constants for PCI-9111 */
/*------------------------*/
/*Dual Interrupt Mode*/
#define P9111_INT1_EOC 0
#define P9111_INT1_FIFO_HF 1
#define P9111_INT2_PACER 0
#define P9111_INT2_EXT_TRG 1
/*Channel Count*/
#define P9111_CHANNEL_DO 0
#define P9111_CHANNEL_EDO 1
#define P9111_CHANNEL_DI 0
#define P9111_CHANNEL_EDI 1
/*EDO function*/
#define P9111_EDO_INPUT 1
#define P9111_EDO_OUT_EDO 2
#define P9111_EDO_OUT_CHN 3
/*Trigger Mode*/
#define P9111_TRGMOD_SOFT 0x00
#define P9111_TRGMOD_PRE 0x01
#define P9111_TRGMOD_POST 0x02
/*AO Setting*/
#define P9111_AO_UNIPOLAR 0
#define P9111_AO_BIPOLAR 1
/*------------------------*/
/* Constants for PCI-9118 */
/*------------------------*/
#define P9118_AI_BiPolar 0x00
#define P9118_AI_UniPolar 0x01
#define P9118_AI_SingEnded 0x00
#define P9118_AI_Differential 0x02
#define P9118_AI_ExtG 0x04
#define P9118_AI_ExtTrig 0x08
#define P9118_AI_DtrgNegative 0x00
#define P9118_AI_DtrgPositive 0x10
#define P9118_AI_EtrgNegative 0x00
#define P9118_AI_EtrgPositive 0x20
#define P9118_AI_BurstModeEn 0x40
#define P9118_AI_SampleHold 0x80
#define P9118_AI_PostTrgEn 0x100
#define P9118_AI_AboutTrgEn 0x200
/*------------------------*/
/* Constants for PCI-9116 */
/*------------------------*/
#define P9116_AI_LocalGND 0x00
#define P9116_AI_UserCMMD 0x01
#define P9116_AI_SingEnded 0x00
#define P9116_AI_Differential 0x02
#define P9116_AI_BiPolar 0x00
#define P9116_AI_UniPolar 0x04
#define P9116_TRGMOD_SOFT 0x00
#define P9116_TRGMOD_POST 0x10
#define P9116_TRGMOD_DELAY 0x20
#define P9116_TRGMOD_PRE 0x30
#define P9116_TRGMOD_MIDL 0x40
#define P9116_AI_TrgPositive 0x00
#define P9116_AI_TrgNegative 0x80
#define P9116_AI_ExtTimeBase 0x100
#define P9116_AI_IntTimeBase 0x000
#define P9116_AI_DlyInSamples 0x200
#define P9116_AI_DlyInTimebase 0x000
#define P9116_AI_ReTrigEn 0x400
#define P9116_AI_MCounterEn 0x800
#define P9116_AI_SoftPolling 0x0000
#define P9116_AI_INT 0x1000
#define P9116_AI_DMA 0x2000
/*------------------------*/
/* Constants for PCI-9812 */
/*------------------------*/
/*Trigger Mode*/
#define P9812_TRGMOD_SOFT 0x00
#define P9812_TRGMOD_POST 0x01
#define P9812_TRGMOD_PRE 0x02
#define P9812_TRGMOD_DELAY 0x03
#define P9812_TRGMOD_MIDL 0x04
#define P9812_AIEvent_Manual 0x80
/*Trigger Source*/
#define P9812_TRGSRC_CH0 0x00
#define P9812_TRGSRC_CH1 0x08
#define P9812_TRGSRC_CH2 0x10
#define P9812_TRGSRC_CH3 0x18
#define P9812_TRGSRC_EXT_DIG 0x20
/*Trigger Polarity*/
#define P9812_TRGSLP_POS 0x00
#define P9812_TRGSLP_NEG 0x40
/*Frequency Selection*/
#define P9812_AD2_GT_PCI 0x80
#define P9812_AD2_LT_PCI 0x00
/*Clock Source*/
#define P9812_CLKSRC_INT 0x000
#define P9812_CLKSRC_EXT_SIN 0x100
#define P9812_CLKSRC_EXT_DIG 0x200
/*------------------------*/
/* Constants for PCI-9221 */
/*------------------------*/
/*Input Type*/
#define P9221_AI_SingEnded 0x0
#define P9221_AI_NonRef_SingEnded 0x1
#define P9221_AI_Differential 0x2
/*Trigger Mode*/
#define P9221_TRGMOD_SOFT 0x00
#define P9221_TRGMOD_ExtD 0x08
/*Trigger Source*/
#define P9221_TRGSRC_GPI0 0x00
#define P9221_TRGSRC_GPI1 0x01
#define P9221_TRGSRC_GPI2 0x02
#define P9221_TRGSRC_GPI3 0x03
#define P9221_TRGSRC_GPI4 0x04
#define P9221_TRGSRC_GPI5 0x05
#define P9221_TRGSRC_GPI6 0x06
#define P9221_TRGSRC_GPI7 0x07
/*Trigger Polarity*/
#define P9221_AI_TrgPositive 0x00
#define P9221_AI_TrgNegative 0x10
/*TimeBase Mode*/
#define P9221_AI_IntTimeBase 0x00
#define P9221_AI_ExtTimeBase 0x80
/*TimeBase Source*/
#define P9221_TimeBaseSRC_GPI0 0x00
#define P9221_TimeBaseSRC_GPI1 0x10
#define P9221_TimeBaseSRC_GPI2 0x20
#define P9221_TimeBaseSRC_GPI3 0x30
#define P9221_TimeBaseSRC_GPI4 0x40
#define P9221_TimeBaseSRC_GPI5 0x50
#define P9221_TimeBaseSRC_GPI6 0x60
#define P9221_TimeBaseSRC_GPI7 0x70
/*EEPROM*/
#define EEPROM_DEFAULT_BANK 0
#define EEPROM_USER_BANK1 1
/*---------------*/
/* Timer/Counter */
/*---------------*/
/*Counter Mode(8254)*/
#define TOGGLE_OUTPUT 0
#define PROG_ONE_SHOT 1
#define RATE_GENERATOR 2
#define SQ_WAVE_RATE_GENERATOR 3
#define SOFT_TRIG 4
#define HARD_TRIG 5
/*16-bit binary or 4-decade BCD counter*/
#define BIN 0
#define BCD 1
/*-------------------------------*/
/* General Purpose Timer/Counter */
/*-------------------------------*/
/*Counter Mode*/
#define General_Counter 0x00
#define Pulse_Generation 0x01
/*GPTC clock source*/
#define GPTC_CLKSRC_EXT 0x08
#define GPTC_CLKSRC_INT 0x00
#define GPTC_GATESRC_EXT 0x10
#define GPTC_GATESRC_INT 0x00
#define GPTC_UPDOWN_SELECT_EXT 0x20
#define GPTC_UPDOWN_SELECT_SOFT 0x00
#define GPTC_UP_CTR 0x40
#define GPTC_DOWN_CTR 0x00
#define GPTC_ENABLE 0x80
#define GPTC_DISABLE 0x00
/*-------------------------------------------------*/
/* General Purpose Timer/Counter for PCI-922x/6202 */
/*-------------------------------------------------*/
/*Counter Mode*/
#define SimpleGatedEventCNT 0x01
#define SinglePeriodMSR 0x02
#define SinglePulseWidthMSR 0x03
#define SingleGatedPulseGen 0x04
#define SingleTrigPulseGen 0x05
#define RetrigSinglePulseGen 0x06
#define SingleTrigContPulseGen 0x07
#define ContGatedPulseGen 0x08
#define EdgeSeparationMSR 0x09
#define SingleTrigContPulseGenPWM 0x0a
#define ContGatedPulseGenPWM 0x0b
#define CW_CCW_Encoder 0x0c
#define x1_AB_Phase_Encoder 0x0d
#define x2_AB_Phase_Encoder 0x0e
#define x4_AB_Phase_Encoder 0x0f
#define Phase_Z 0x10
/*GPTC clock source*/
#define GPTC_CLK_SRC_Ext 0x01
#define GPTC_CLK_SRC_Int 0x00
#define GPTC_GATE_SRC_Ext 0x02
#define GPTC_GATE_SRC_Int 0x00
#define GPTC_UPDOWN_Ext 0x04
#define GPTC_UPDOWN_Int 0x00
/*GPTC clock polarity*/
#define GPTC_CLKSRC_LACTIVE 0x01
#define GPTC_CLKSRC_HACTIVE 0x00
#define GPTC_GATE_LACTIVE 0x02
#define GPTC_GATE_HACTIVE 0x00
#define GPTC_UPDOWN_LACTIVE 0x04
#define GPTC_UPDOWN_HACTIVE 0x00
#define GPTC_OUTPUT_LACTIVE 0x08
#define GPTC_OUTPUT_HACTIVE 0x00
/*GPTC OP Parameter*/
#define IntGate 0x0
#define IntUpDnCTR 0x1
#define IntENABLE 0x2
/*Z-Phase*/
#define GPTC_EZ0_ClearPhase0 0x0
#define GPTC_EZ0_ClearPhase1 0x1
#define GPTC_EZ0_ClearPhase2 0x2
#define GPTC_EZ0_ClearPhase3 0x3
/*Z-Mode*/
#define GPTC_EZ0_ClearMode0 0x0
#define GPTC_EZ0_ClearMode1 0x1
#define GPTC_EZ0_ClearMode2 0x2
#define GPTC_EZ0_clearMode3 0x3
/*----------------*/
/* Watchdog Timer */
/*----------------*/
/*Counter action*/
#define WDT_DISARM 0
#define WDT_ARM 1
#define WDT_RESTART 2
/*Pattern ID*/
#define INIT_PTN 0
#define EMGSHDN_PTN 1
/*Pattern ID for 7442/7444*/
#define INIT_PTN_CH0 0
#define INIT_PTN_CH1 1
#define INIT_PTN_CH2 2
#define INIT_PTN_CH3 3
#define SAFTOUT_PTN_CH0 4
#define SAFTOUT_PTN_CH1 5
#define SAFTOUT_PTN_CH2 6
#define SAFTOUT_PTN_CH3 7
/*----------------------------------------------------------*/
/* Previous renamed functions re-directed for compatibility */
/*----------------------------------------------------------*/
#define AI_VScale AI_VoltScale
#define AO_VScale AO_VoltScale
#define CTR_Reset CTR_Clear
/*--------------------------------------*/
/* DAQ Event type for the event message */
/*--------------------------------------*/
#define AIEnd 0
#define AOEnd 0
#define DIEnd 0
#define DOEnd 0
#define DBEvent 1
#define TrigEvent 2
/*------------------------*/
/* Constants for PCI-9524 */
/*------------------------*/
/*AI Interrupt*/
#define P9524_INT_LC_EOC 0x2 //06/10/08
#define P9524_INT_GP_EOC 0x3 //06/10/08
/*DSP Constants*/
#define P9524_SPIKE_REJ_DISABLE 0x0
#define P9524_SPIKE_REJ_ENABLE 0x1
/*Transfer Mode*/
#define P9524_AI_XFER_POLL 0x0
#define P9524_AI_XFER_DMA 0x1
/*Poll All Channels*/
#define P9524_AI_POLL_ALLCHANNELS 8
#define P9524_AI_POLLSCANS_CH0_CH3 8
#define P9524_AI_POLLSCANS_CH0_CH2 9
#define P9524_AI_POLLSCANS_CH0_CH1 10
/*ADC Sampling Rate*/
#define P9524_ADC_30K_SPS 0
#define P9524_ADC_15K_SPS 1
#define P9524_ADC_7K5_SPS 2
#define P9524_ADC_3K75_SPS 3
#define P9524_ADC_2K_SPS 4
#define P9524_ADC_1K_SPS 5
#define P9524_ADC_500_SPS 6
#define P9524_ADC_100_SPS 7
#define P9524_ADC_60_SPS 8
#define P9524_ADC_50_SPS 9
#define P9524_ADC_30_SPS 10
#define P9524_ADC_25_SPS 11
#define P9524_ADC_15_SPS 12
#define P9524_ADC_10_SPS 13
#define P9524_ADC_5_SPS 14
#define P9524_ADC_2R5_SPS 15
/*ConfigCtrl Constants*/
#define P9524_VEX_Range_2R5V 0x0
#define P9524_VEX_Range_10V 0x1
#define P9524_VEX_Sence_Local 0x0
#define P9524_VEX_Sence_Remote 0x2
#define P9524_AI_AZMode 0x4
#define P9524_AI_BufAutoReset 0x8
#define P9524_AI_EnEOCInt 0x10 //06/10/08
/*Trigger Constants*/
#define P9524_TRGMOD_POST 0x00
#define P9524_TRGSRC_SOFT 0x00
#define P9524_TRGSRC_ExtD 0x01
#define P9524_TRGSRC_SSI 0x02
#define P9524_TRGSRC_QD0 0x03
#define P9524_TRGSRC_PG0 0x04
#define P9524_AI_TrgPositive 0x00
#define P9524_AI_TrgNegative 0x08
/*Group*/
#define P9524_AI_LC_Group 0
#define P9524_AI_GP_Group 1
/*Channel*/
#define P9524_AI_LC_CH0 0
#define P9524_AI_LC_CH1 1
#define P9524_AI_LC_CH2 2
#define P9524_AI_LC_CH3 3
#define P9524_AI_GP_CH0 4
#define P9524_AI_GP_CH1 5
#define P9524_AI_GP_CH2 6
#define P9524_AI_GP_CH3 7
/*Pulse Generation and Quadrature Decoder*/
#define P9524_CTR_PG0 0
#define P9524_CTR_PG1 1
#define P9524_CTR_PG2 2
#define P9524_CTR_QD0 3
#define P9524_CTR_QD1 4
#define P9524_CTR_QD2 5
#define P9524_CTR_INTCOUNTER 6
/*Counter Mode*/
#define P9524_PulseGen_OUTDIR_N 0
#define P9524_PulseGen_OUTDIR_R 1
#define P9524_PulseGen_CW 0
#define P9524_PulseGen_CCW 2
#define P9524_x4_AB_Phase_Decoder 3
#define P9524_Timer 4
/*Counter Op*/
#define P9524_CTR_Enable 0
/*Event Mode*/
#define P9524_Event_Timer 0
/*AO*/
#define P9524_AO_CH0_1 0
/*------------------------*/
/* Constants for PCI-6202 */
/*------------------------*/
/*DIO channel*/
#define P6202_ISO0 0
#define P6202_TTL0 1
/*GPTC/Encoder channel*/
#define P6202_GPTC0 0x00
#define P6202_GPTC1 0x01
#define P6202_ENCODER0 0x02
#define P6202_ENCODER1 0x03
#define P6202_ENCODER2 0x04
/*DA control constant*/
#define P6202_DA_WRSRC_Int 0x00
#define P6202_DA_WRSRC_AFI0 0x01
#define P6202_DA_WRSRC_SSI 0x02
#define P6202_DA_WRSRC_AFI1 0x03
/*DA trigger constant*/
#define P6202_DA_TRGSRC_SOFT 0x00
#define P6202_DA_TRGSRC_AFI0 0x01
#define P6202_DA_TRGSRC_SSI 0x02
#define P6202_DA_TRGSRC_AFI1 0x03
#define P6202_DA_TRGMOD_POST 0x00
#define P6202_DA_TRGMOD_DELAY 0x04
#define P6202_DA_ReTrigEn 0x20
#define P6202_DA_DLY2En 0x100
/*SSI signal code*/
#define P6202_SSI_DA_CONV 0x04
#define P6202_SSI_DA_TRIG 0x40
/*Encoder constant*/
#define P6202_EVT_TYPE_EPT0 0x00
#define P6202_EVT_TYPE_EPT1 0x01
#define P6202_EVT_TYPE_EPT2 0x02
#define P6202_EVT_TYPE_EZC0 0x03
#define P6202_EVT_TYPE_EZC1 0x04
#define P6202_EVT_TYPE_EZC2 0x05
#define P6202_EVT_MOD_EPT 0x00
#define P6202_EPT_PULWIDTH_200us 0x00
#define P6202_EPT_PULWIDTH_2ms 0x01
#define P6202_EPT_PULWIDTH_20ms 0x02
#define P6202_EPT_PULWIDTH_200ms 0x03
#define P6202_EPT_TRGOUT_CALLBACK 0x04
#define P6202_EPT_TRGOUT_AFI 0x08
#define P6202_ENCODER0_LDATA 0x05
#define P6202_ENCODER1_LDATA 0x06
#define P6202_ENCODER2_LDATA 0x07
/*AFI Port*/
#define P6202_AFI_0 0
#define P6202_AFI_1 1
/*AFI Mode*/
#define P6202_AFI_SYNCIntTrigOut 0
/*AFI Trigout Length*/
#define P6202_AFI_SYNCTrig_200ns 0
#define P6202_AFI_SYNCTrig_2ms 1
#define P6202_AFI_SYNCTrig_20ms 2
#define P6202_AFI_SYNCTrig_200ms 3
/*------------------------*/
/* Constants for PCI-922x */
/*------------------------*/
/*
* AI Constants
*/
/*Input Type*/
#define P922x_AI_SingEnded 0x00
#define P922x_AI_NonRef_SingEnded 0x01
#define P922x_AI_Differential 0x02
/*Conversion Source*/
#define P922x_AI_CONVSRC_INT 0x00
#define P922x_AI_CONVSRC_GPI0 0x10
#define P922x_AI_CONVSRC_GPI1 0x20
#define P922x_AI_CONVSRC_GPI2 0x30
#define P922x_AI_CONVSRC_GPI3 0x40
#define P922x_AI_CONVSRC_GPI4 0x50
#define P922x_AI_CONVSRC_GPI5 0x60
#define P922x_AI_CONVSRC_GPI6 0x70
#define P922x_AI_CONVSRC_GPI7 0x80
#define P922x_AI_CONVSRC_SSI1 0x90
#define P922x_AI_CONVSRC_SSI 0x90
/*Trigger Mode*/
#define P922x_AI_TRGMOD_POST 0x00
#define P922x_AI_TRGMOD_GATED 0x01
/*Trigger Source*/
#define P922x_AI_TRGSRC_SOFT 0x00
#define P922x_AI_TRGSRC_GPI0 0x10
#define P922x_AI_TRGSRC_GPI1 0x20
#define P922x_AI_TRGSRC_GPI2 0x30
#define P922x_AI_TRGSRC_GPI3 0x40
#define P922x_AI_TRGSRC_GPI4 0x50
#define P922x_AI_TRGSRC_GPI5 0x60
#define P922x_AI_TRGSRC_GPI6 0x70
#define P922x_AI_TRGSRC_GPI7 0x80
#define P922x_AI_TRGSRC_SSI5 0x90
#define P922x_AI_TRGSRC_SSI 0x90
/*Trigger Polarity*/
#define P922x_AI_TrgPositive 0x000
#define P922x_AI_TrgNegative 0x100
/*ReTrigger*/
#define P922x_AI_EnReTigger 0x200
/*
* AO Constants
*/
/*Conversion Source*/
#define P922x_AO_CONVSRC_INT 0x00
#define P922x_AO_CONVSRC_GPI0 0x01
#define P922x_AO_CONVSRC_GPI1 0x02
#define P922x_AO_CONVSRC_GPI2 0x03
#define P922x_AO_CONVSRC_GPI3 0x04
#define P922x_AO_CONVSRC_GPI4 0x05
#define P922x_AO_CONVSRC_GPI5 0x06
#define P922x_AO_CONVSRC_GPI6 0x07
#define P922x_AO_CONVSRC_GPI7 0x08
#define P922x_AO_CONVSRC_SSI2 0x09
#define P922x_AO_CONVSRC_SSI 0x09
/*Trigger Mode*/
#define P922x_AO_TRGMOD_POST 0x00
#define P922x_AO_TRGMOD_DELAY 0x01
/*Trigger Source*/
#define P922x_AO_TRGSRC_SOFT 0x00
#define P922x_AO_TRGSRC_GPI0 0x10
#define P922x_AO_TRGSRC_GPI1 0x20
#define P922x_AO_TRGSRC_GPI2 0x30
#define P922x_AO_TRGSRC_GPI3 0x40
#define P922x_AO_TRGSRC_GPI4 0x50
#define P922x_AO_TRGSRC_GPI5 0x60
#define P922x_AO_TRGSRC_GPI6 0x70
#define P922x_AO_TRGSRC_GPI7 0x80
#define P922x_AO_TRGSRC_SSI6 0x90
#define P922x_AO_TRGSRC_SSI 0x90
/*Trigger Polarity*/
#define P922x_AO_TrgPositive 0x000
#define P922x_AO_TrgNegative 0x100
#define P922x_AO_EnReTigger 0x200
#define P922x_AO_EnDelay2 0x400
/*
* DI Constants
*/
/*Conversion Source*/
#define P922x_DI_CONVSRC_INT 0x00
#define P922x_DI_CONVSRC_GPI0 0x01
#define P922x_DI_CONVSRC_GPI1 0x02
#define P922x_DI_CONVSRC_GPI2 0x03
#define P922x_DI_CONVSRC_GPI3 0x04
#define P922x_DI_CONVSRC_GPI4 0x05
#define P922x_DI_CONVSRC_GPI5 0x06
#define P922x_DI_CONVSRC_GPI6 0x07
#define P922x_DI_CONVSRC_GPI7 0x08
#define P922x_DI_CONVSRC_ADCONV 0x09
#define P922x_DI_CONVSRC_DACONV 0x0A
/*Trigger Mode*/
#define P922x_DI_TRGMOD_POST 0x00
/*Trigger Source*/
#define P922x_DI_TRGSRC_SOFT 0x00
#define P922x_DI_TRGSRC_GPI0 0x10
#define P922x_DI_TRGSRC_GPI1 0x20
#define P922x_DI_TRGSRC_GPI2 0x30
#define P922x_DI_TRGSRC_GPI3 0x40
#define P922x_DI_TRGSRC_GPI4 0x50
#define P922x_DI_TRGSRC_GPI5 0x60
#define P922x_DI_TRGSRC_GPI6 0x70