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axi_dmac: Remove unused pause signal from address generator
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The pause signal is not used inside the address generator module. Remove
it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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larsclausen authored and Csomi committed Apr 11, 2018
1 parent 2b2c1f6 commit 05e8604
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Showing 4 changed files with 6 additions and 15 deletions.
1 change: 0 additions & 1 deletion library/axi_dmac/address_generator.v
Original file line number Diff line number Diff line change
Expand Up @@ -57,7 +57,6 @@ module dmac_address_generator #(
input eot,

input enable,
input pause,
output reg enabled,

input addr_ready,
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2 changes: 0 additions & 2 deletions library/axi_dmac/dest_axi_mm.v
Original file line number Diff line number Diff line change
Expand Up @@ -52,7 +52,6 @@ module dmac_dest_mm_axi #(

input enable,
output enabled,
input pause,
input sync_id,
output sync_id_ret,

Expand Down Expand Up @@ -139,7 +138,6 @@ dmac_address_generator #(

.enable(enable),
.enabled(address_enabled),
.pause(pause),

.id(address_id),
.request_id(request_id),
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16 changes: 6 additions & 10 deletions library/axi_dmac/request_arb.v
Original file line number Diff line number Diff line change
Expand Up @@ -192,12 +192,10 @@ wire sync_id_ret_src;

wire dest_enable;
wire dest_enabled;
wire dest_pause;
wire dest_sync_id;
wire dest_sync_id_ret;
wire src_enable;
wire src_enabled;
wire src_pause;
wire src_sync_id;
wire src_sync_id_ret;

Expand Down Expand Up @@ -411,7 +409,6 @@ dmac_dest_mm_axi #(

.enable(dest_enable),
.enabled(dest_enabled),
.pause(dest_pause),

.req_valid(dest_req_valid),
.req_ready(dest_req_ready),
Expand Down Expand Up @@ -623,7 +620,6 @@ dmac_src_mm_axi #(
.m_axi_aclk(m_src_axi_aclk),
.m_axi_aresetn(src_resetn),

.pause(src_pause),
.enable(src_enable),
.enabled(src_enabled),
.sync_id(src_sync_id),
Expand Down Expand Up @@ -1082,13 +1078,13 @@ dmac_request_generator #(
);

sync_bits #(
.NUM_OF_BITS(3),
.NUM_OF_BITS(2),
.ASYNC_CLK(ASYNC_CLK_DEST_REQ)
) i_sync_control_dest (
.out_clk(dest_clk),
.out_resetn(dest_resetn),
.in({do_enable, pause, sync_id}),
.out({dest_enable, dest_pause, dest_sync_id})
.in({do_enable, sync_id}),
.out({dest_enable, dest_sync_id})
);

sync_bits #(
Expand All @@ -1102,13 +1098,13 @@ sync_bits #(
);

sync_bits #(
.NUM_OF_BITS(3),
.NUM_OF_BITS(2),
.ASYNC_CLK(ASYNC_CLK_REQ_SRC)
) i_sync_control_src (
.out_clk(src_clk),
.out_resetn(src_resetn),
.in({do_enable, pause, sync_id}),
.out({src_enable, src_pause, src_sync_id})
.in({do_enable, sync_id}),
.out({src_enable, src_sync_id})
);

sync_bits #(
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2 changes: 0 additions & 2 deletions library/axi_dmac/src_axi_mm.v
Original file line number Diff line number Diff line change
Expand Up @@ -52,7 +52,6 @@ module dmac_src_mm_axi #(

input enable,
output enabled,
input pause,
input sync_id,
output sync_id_ret,

Expand Down Expand Up @@ -131,7 +130,6 @@ dmac_address_generator #(

.enable(enable),
.enabled(address_enabled),
.pause(pause),
.sync_id(sync_id),

.request_id(request_id),
Expand Down

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