axi_dmac: Update IP with the new util_axis_fifo

Update instantiation, false path definitions and make file.
analogdevicesinc · Dec 4, 2020 · f7b8a2d · f7b8a2d
1 parent eb7e533
commit f7b8a2d
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Showing 6 changed files with 30 additions and 24 deletions.
diff --git a/library/axi_dmac/Makefile b/library/axi_dmac/Makefile
@@ -47,7 +47,7 @@ XILINX_DEPS += ../interfaces/fifo_wr_rtl.xml
 XILINX_LIB_DEPS += util_axis_fifo
 XILINX_LIB_DEPS += util_cdc
 
-INTEL_DEPS += ../util_axis_fifo/address_sync.v
+INTEL_DEPS += ../util_axis_fifo/util_axis_fifo_address_generator.v
 INTEL_DEPS += ../util_axis_fifo/util_axis_fifo.v
 INTEL_DEPS += ../util_cdc/sync_bits.v
 INTEL_DEPS += ../util_cdc/sync_event.v

diff --git a/library/axi_dmac/axi_dmac_constr.ttcl b/library/axi_dmac/axi_dmac_constr.ttcl
@@ -38,13 +38,13 @@ set_false_path -quiet \
 set_max_delay -quiet -datapath_only \
 	-from $req_clk \
 	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_src_req_fifo/i_waddr_sync* && IS_SEQUENTIAL}] \
+		-filter {NAME =~ *i_src_req_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \
 	[get_property -min PERIOD $req_clk]
 
 set_max_delay -quiet -datapath_only \
 	-from $src_clk \
 	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_src_req_fifo/i_raddr_sync* && IS_SEQUENTIAL}] \
+		-filter {NAME =~ *i_src_req_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \
 	[get_property -min PERIOD $src_clk]
 
 set_max_delay -quiet -datapath_only \
@@ -63,13 +63,13 @@ set_max_delay -quiet -datapath_only \
 set_max_delay -quiet -datapath_only \
 	-from $src_clk \
 	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_rewind_req_fifo/i_waddr_sync* && IS_SEQUENTIAL}] \
+		-filter {NAME =~ *i_rewind_req_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \
 	[get_property -min PERIOD $src_clk]
 
 set_max_delay -quiet -datapath_only \
 	-from $req_clk \
 	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_rewind_req_fifo/i_raddr_sync* && IS_SEQUENTIAL}] \
+		-filter {NAME =~ *i_rewind_req_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \
 	[get_property -min PERIOD $req_clk]
 
 set_max_delay -quiet -datapath_only \
@@ -109,13 +109,13 @@ set_false_path -quiet \
 set_max_delay -quiet -datapath_only \
 	-from $dest_clk \
 	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_dest_response_fifo/i_waddr_sync* && IS_SEQUENTIAL}] \
+		-filter {NAME =~ *i_dest_response_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \
 	[get_property -min PERIOD $dest_clk]
 
 set_max_delay -quiet -datapath_only \
 	-from $req_clk \
 	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_dest_response_fifo/i_raddr_sync* && IS_SEQUENTIAL}] \
+		-filter {NAME =~ *i_dest_response_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \
 	[get_property -min PERIOD $req_clk]
 set_max_delay -quiet -datapath_only \
 	-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
@@ -153,13 +153,13 @@ set_max_delay -quiet -datapath_only \
 set_max_delay -quiet -datapath_only \
 	-from $src_clk \
 	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_dest_req_fifo/i_waddr_sync* && IS_SEQUENTIAL}] \
+		-filter {NAME =~ *i_dest_req_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \
 	[get_property -min PERIOD $src_clk]
 
 set_max_delay -quiet -datapath_only \
 	-from $dest_clk \
 	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_dest_req_fifo/i_raddr_sync* && IS_SEQUENTIAL}] \
+		-filter {NAME =~ *i_dest_req_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \
 	[get_property -min PERIOD $dest_clk]
 
 set_max_delay -quiet -datapath_only \
@@ -171,13 +171,13 @@ set_max_delay -quiet -datapath_only \
 set_max_delay -quiet -datapath_only \
 	-from $src_clk \
 	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_src_dest_bl_fifo/i_waddr_sync* && IS_SEQUENTIAL}] \
+		-filter {NAME =~ *i_src_dest_bl_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \
 	[get_property -min PERIOD $src_clk]
 
 set_max_delay -quiet -datapath_only \
 	-from $dest_clk \
 	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-		-filter {NAME =~ *i_src_dest_bl_fifo/i_raddr_sync* && IS_SEQUENTIAL}] \
+		-filter {NAME =~ *i_src_dest_bl_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \
 	[get_property -min PERIOD $dest_clk]
 
 set_max_delay -quiet -datapath_only \

diff --git a/library/axi_dmac/axi_dmac_hw.tcl b/library/axi_dmac/axi_dmac_hw.tcl
@@ -19,7 +19,7 @@ ad_ip_files axi_dmac [list \
   $ad_hdl_dir/library/util_cdc/sync_event.v \
   $ad_hdl_dir/library/common/up_axi.v \
   $ad_hdl_dir/library/util_axis_fifo/util_axis_fifo.v \
-  $ad_hdl_dir/library/util_axis_fifo/address_sync.v \
+  $ad_hdl_dir/library/util_axis_fifo/util_axis_fifo_address_generator.v \
   $ad_hdl_dir/library/common/ad_mem_asym.v \
   inc_id.vh \
   resp.vh \

diff --git a/library/axi_dmac/axi_dmac_regmap_request.v b/library/axi_dmac/axi_dmac_regmap_request.v
@@ -298,7 +298,7 @@ util_axis_fifo #(
   .s_axis_aresetn(ctrl_enable),
   .s_axis_valid(up_tlf_s_valid),
   .s_axis_ready(up_tlf_s_ready),
-  .s_axis_empty(),
+  .s_axis_full(),
   .s_axis_data({up_transfer_id_eot_d, up_measured_transfer_length}),
   .s_axis_room(),
 
@@ -307,7 +307,8 @@ util_axis_fifo #(
   .m_axis_valid(up_tlf_valid),
   .m_axis_ready(up_tlf_rd & up_tlf_valid),
   .m_axis_data(up_tlf_data),
-  .m_axis_level()
+  .m_axis_level(),
+  .m_axis_empty ()
 );
 
 endmodule
diff --git a/library/axi_dmac/axi_dmac_response_manager.v b/library/axi_dmac/axi_dmac_response_manager.v
@@ -120,7 +120,7 @@ util_axis_fifo #(
   .s_axis_aresetn(dest_resetn),
   .s_axis_valid(dest_response_valid),
   .s_axis_ready(dest_response_ready),
-  .s_axis_empty(),
+  .s_axis_full(),
   .s_axis_data({dest_response_data_burst_length,
                 dest_response_partial,
                 dest_response_resp_eot}),
@@ -133,7 +133,8 @@ util_axis_fifo #(
   .m_axis_data({response_dest_data_burst_length,
                 response_dest_partial,
                 response_dest_resp_eot}),
-  .m_axis_level()
+  .m_axis_level(),
+  .m_axis_empty()
 );
 
 always @(posedge req_clk)

diff --git a/library/axi_dmac/request_arb.v b/library/axi_dmac/request_arb.v
@@ -431,7 +431,7 @@ util_axis_fifo #(
   .s_axis_aresetn(src_resetn),
   .s_axis_valid(src_bl_valid),
   .s_axis_ready(src_bl_ready),
-  .s_axis_empty(),
+  .s_axis_full(),
   .s_axis_data(src_burst_length),
   .s_axis_room(),
 
@@ -440,7 +440,8 @@ util_axis_fifo #(
   .m_axis_valid(dest_bl_valid),
   .m_axis_ready(dest_bl_ready),
   .m_axis_data(dest_src_burst_length),
-  .m_axis_level()
+  .m_axis_level(),
+  .m_axis_empty()
 );
 
 // Adapt burst length from source width to destination width by either
@@ -767,7 +768,7 @@ util_axis_fifo #(
   .s_axis_aresetn(src_resetn),
   .s_axis_valid(rewind_req_valid),
   .s_axis_ready(rewind_req_ready),
-  .s_axis_empty(),
+  .s_axis_full(),
   .s_axis_data(rewind_req_data),
   .s_axis_room(),
 
@@ -776,7 +777,8 @@ util_axis_fifo #(
   .m_axis_valid(req_rewind_req_valid),
   .m_axis_ready(req_rewind_req_ready),
   .m_axis_data(req_rewind_req_data),
-  .m_axis_level()
+  .m_axis_level(),
+  .m_axis_empty()
 );
 
 end else begin
@@ -1028,7 +1030,7 @@ util_axis_fifo #(
   .s_axis_aresetn(src_resetn),
   .s_axis_valid(src_dest_valid_hs_masked),
   .s_axis_ready(src_dest_ready_hs),
-  .s_axis_empty(),
+  .s_axis_full(),
   .s_axis_data({
     src_req_dest_address_cur,
     src_req_xlast_cur
@@ -1043,7 +1045,8 @@ util_axis_fifo #(
     dest_req_dest_address,
     dest_req_xlast
   }),
-  .m_axis_level()
+  .m_axis_level(),
+  .m_axis_empty()
 );
 
 util_axis_fifo #(
@@ -1055,7 +1058,7 @@ util_axis_fifo #(
   .s_axis_aresetn(req_resetn),
   .s_axis_valid(req_src_valid),
   .s_axis_ready(req_src_ready),
-  .s_axis_empty(),
+  .s_axis_full(),
   .s_axis_data({
     req_dest_address,
     req_src_address,
@@ -1077,7 +1080,8 @@ util_axis_fifo #(
     src_req_sync_transfer_start,
     src_req_xlast
   }),
-  .m_axis_level()
+  .m_axis_level(),
+  .m_axis_empty()
 );
 
 // Save the descriptor in the source clock domain since the submission to