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design.json
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design.json
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{
"info": {
"GRID_X_MAX": 58,
"GRID_X_MIN": 10,
"GRID_Y_MAX": 51,
"GRID_Y_MIN": 0
},
"ports": [
{
"name": "clk",
"node": "CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0",
"pin": "W5",
"type": "clk",
"wire": "HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0"
},
{
"name": "din[0]",
"node": "INT_L_X0Y102/EE2BEG2",
"pin": "V17",
"type": "in",
"wire": "VBRK_X9Y107/VBRK_EE2A2",
"wires_outside_roi": [
"BRKH_INT_X0Y49/BRKH_INT_L_LV1",
"BRKH_INT_X0Y99/BRKH_INT_NN6C2",
"CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_1",
"CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_2",
"HCLK_L_X4Y26/HCLK_LV12",
"HCLK_L_X4Y78/HCLK_LV8",
"INT_INTERFACE_R_X1Y102/INT_INTERFACE_EE2A2",
"INT_L_X0Y11/LOGIC_OUTS_L18",
"INT_L_X0Y11/NR1BEG0",
"INT_L_X0Y12/LV_L0",
"INT_L_X0Y12/NR1END0",
"INT_L_X0Y13/LV_L1",
"INT_L_X0Y14/LV_L2",
"INT_L_X0Y15/LV_L3",
"INT_L_X0Y16/LV_L4",
"INT_L_X0Y17/LV_L5",
"INT_L_X0Y18/LV_L6",
"INT_L_X0Y19/LV_L7",
"INT_L_X0Y20/LV_L8",
"INT_L_X0Y21/LV_L9",
"INT_L_X0Y22/LV_L10",
"INT_L_X0Y23/LV_L11",
"INT_L_X0Y24/LV_L12",
"INT_L_X0Y25/LV_L13",
"INT_L_X0Y26/LV_L14",
"INT_L_X0Y27/LV_L15",
"INT_L_X0Y28/LV_L16",
"INT_L_X0Y29/LV_L17",
"INT_L_X0Y30/LV_L0",
"INT_L_X0Y30/LV_L18",
"INT_L_X0Y31/LV_L1",
"INT_L_X0Y32/LV_L2",
"INT_L_X0Y33/LV_L3",
"INT_L_X0Y34/LV_L4",
"INT_L_X0Y35/LV_L5",
"INT_L_X0Y36/LV_L6",
"INT_L_X0Y37/LV_L7",
"INT_L_X0Y38/LV_L8",
"INT_L_X0Y39/LV_L9",
"INT_L_X0Y40/LV_L10",
"INT_L_X0Y41/LV_L11",
"INT_L_X0Y42/LV_L12",
"INT_L_X0Y43/LV_L13",
"INT_L_X0Y44/LV_L14",
"INT_L_X0Y45/LV_L15",
"INT_L_X0Y46/LV_L16",
"INT_L_X0Y47/LV_L17",
"INT_L_X0Y48/LV_L0",
"INT_L_X0Y48/LV_L18",
"INT_L_X0Y49/LV_L1",
"INT_L_X0Y50/LV_L2",
"INT_L_X0Y51/LV_L3",
"INT_L_X0Y52/LV_L4",
"INT_L_X0Y53/LV_L5",
"INT_L_X0Y54/LV_L6",
"INT_L_X0Y55/LV_L7",
"INT_L_X0Y56/LV_L8",
"INT_L_X0Y57/LV_L9",
"INT_L_X0Y58/LV_L10",
"INT_L_X0Y59/LV_L11",
"INT_L_X0Y60/LV_L12",
"INT_L_X0Y61/LV_L13",
"INT_L_X0Y62/LV_L14",
"INT_L_X0Y63/LV_L15",
"INT_L_X0Y64/LV_L16",
"INT_L_X0Y65/LV_L17",
"INT_L_X0Y66/LV_L0",
"INT_L_X0Y66/LV_L18",
"INT_L_X0Y67/LV_L1",
"INT_L_X0Y68/LV_L2",
"INT_L_X0Y69/LV_L3",
"INT_L_X0Y70/LV_L4",
"INT_L_X0Y71/LV_L5",
"INT_L_X0Y72/LV_L6",
"INT_L_X0Y73/LV_L7",
"INT_L_X0Y74/LV_L8",
"INT_L_X0Y75/LV_L9",
"INT_L_X0Y76/LV_L10",
"INT_L_X0Y77/LV_L11",
"INT_L_X0Y78/LV_L12",
"INT_L_X0Y79/LV_L13",
"INT_L_X0Y80/LV_L14",
"INT_L_X0Y81/LV_L15",
"INT_L_X0Y82/LV_L16",
"INT_L_X0Y83/LV_L17",
"INT_L_X0Y84/LVB_L0",
"INT_L_X0Y84/LV_L18",
"INT_L_X0Y85/LVB_L1",
"INT_L_X0Y86/LVB_L2",
"INT_L_X0Y87/LVB_L3",
"INT_L_X0Y88/LVB_L4",
"INT_L_X0Y89/LVB_L5",
"INT_L_X0Y90/LVB_L6",
"INT_L_X0Y91/LVB_L7",
"INT_L_X0Y92/LVB_L8",
"INT_L_X0Y93/LVB_L9",
"INT_L_X0Y94/LVB_L10",
"INT_L_X0Y95/LVB_L11",
"INT_L_X0Y96/LVB_L12",
"INT_L_X0Y96/NN6BEG2",
"INT_L_X0Y97/NN6A2",
"INT_L_X0Y98/NN6B2",
"INT_L_X0Y99/NN6C2",
"INT_L_X0Y100/NN6D2",
"INT_L_X0Y101/NN6E2",
"INT_L_X0Y102/EE2BEG2",
"INT_L_X0Y102/NN6END2",
"INT_R_X1Y102/EE2A2",
"IO_INT_INTERFACE_L_X0Y11/INT_INTERFACE_LOGIC_OUTS_L18",
"IO_INT_INTERFACE_L_X0Y11/INT_INTERFACE_LOGIC_OUTS_L_B18",
"LIOB33_X0Y11/IOB_IBUF1",
"LIOI3_X0Y11/IOI_ILOGIC1_O",
"LIOI3_X0Y11/IOI_LOGIC_OUTS18_0",
"LIOI3_X0Y11/LIOI_I1",
"LIOI3_X0Y11/LIOI_IBUF1",
"LIOI3_X0Y11/LIOI_ILOGIC1_D",
"L_TERM_INT_X2Y12/TERM_INT_LOGIC_OUTS_L_B18",
"VBRK_X9Y107/VBRK_EE2A2"
]
},
{
"name": "din[1]",
"node": "INT_L_X0Y104/EE2BEG2",
"pin": "V16",
"type": "in",
"wire": "VBRK_X9Y109/VBRK_EE2A2",
"wires_outside_roi": [
"BRKH_INT_X0Y49/BRKH_INT_L_LV0",
"BRKH_INT_X0Y99/BRKH_INT_NN6B2",
"CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_3",
"CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_4",
"HCLK_L_X4Y26/HCLK_LV11",
"HCLK_L_X4Y78/HCLK_LV7",
"INT_INTERFACE_R_X1Y104/INT_INTERFACE_EE2A2",
"INT_L_X0Y12/LOGIC_OUTS_L18",
"INT_L_X0Y12/NR1BEG0",
"INT_L_X0Y13/LV_L0",
"INT_L_X0Y13/NR1END0",
"INT_L_X0Y14/LV_L1",
"INT_L_X0Y15/LV_L2",
"INT_L_X0Y16/LV_L3",
"INT_L_X0Y17/LV_L4",
"INT_L_X0Y18/LV_L5",
"INT_L_X0Y19/LV_L6",
"INT_L_X0Y20/LV_L7",
"INT_L_X0Y21/LV_L8",
"INT_L_X0Y22/LV_L9",
"INT_L_X0Y23/LV_L10",
"INT_L_X0Y24/LV_L11",
"INT_L_X0Y25/LV_L12",
"INT_L_X0Y26/LV_L13",
"INT_L_X0Y27/LV_L14",
"INT_L_X0Y28/LV_L15",
"INT_L_X0Y29/LV_L16",
"INT_L_X0Y30/LV_L17",
"INT_L_X0Y31/LV_L0",
"INT_L_X0Y31/LV_L18",
"INT_L_X0Y32/LV_L1",
"INT_L_X0Y33/LV_L2",
"INT_L_X0Y34/LV_L3",
"INT_L_X0Y35/LV_L4",
"INT_L_X0Y36/LV_L5",
"INT_L_X0Y37/LV_L6",
"INT_L_X0Y38/LV_L7",
"INT_L_X0Y39/LV_L8",
"INT_L_X0Y40/LV_L9",
"INT_L_X0Y41/LV_L10",
"INT_L_X0Y42/LV_L11",
"INT_L_X0Y43/LV_L12",
"INT_L_X0Y44/LV_L13",
"INT_L_X0Y45/LV_L14",
"INT_L_X0Y46/LV_L15",
"INT_L_X0Y47/LV_L16",
"INT_L_X0Y48/LV_L17",
"INT_L_X0Y49/LV_L0",
"INT_L_X0Y49/LV_L18",
"INT_L_X0Y50/LV_L1",
"INT_L_X0Y51/LV_L2",
"INT_L_X0Y52/LV_L3",
"INT_L_X0Y53/LV_L4",
"INT_L_X0Y54/LV_L5",
"INT_L_X0Y55/LV_L6",
"INT_L_X0Y56/LV_L7",
"INT_L_X0Y57/LV_L8",
"INT_L_X0Y58/LV_L9",
"INT_L_X0Y59/LV_L10",
"INT_L_X0Y60/LV_L11",
"INT_L_X0Y61/LV_L12",
"INT_L_X0Y62/LV_L13",
"INT_L_X0Y63/LV_L14",
"INT_L_X0Y64/LV_L15",
"INT_L_X0Y65/LV_L16",
"INT_L_X0Y66/LV_L17",
"INT_L_X0Y67/LV_L0",
"INT_L_X0Y67/LV_L18",
"INT_L_X0Y68/LV_L1",
"INT_L_X0Y69/LV_L2",
"INT_L_X0Y70/LV_L3",
"INT_L_X0Y71/LV_L4",
"INT_L_X0Y72/LV_L5",
"INT_L_X0Y73/LV_L6",
"INT_L_X0Y74/LV_L7",
"INT_L_X0Y75/LV_L8",
"INT_L_X0Y76/LV_L9",
"INT_L_X0Y77/LV_L10",
"INT_L_X0Y78/LV_L11",
"INT_L_X0Y79/LV_L12",
"INT_L_X0Y80/LV_L13",
"INT_L_X0Y81/LV_L14",
"INT_L_X0Y82/LV_L15",
"INT_L_X0Y83/LV_L16",
"INT_L_X0Y84/LV_L17",
"INT_L_X0Y85/LVB_L0",
"INT_L_X0Y85/LV_L18",
"INT_L_X0Y86/LVB_L1",
"INT_L_X0Y87/LVB_L2",
"INT_L_X0Y88/LVB_L3",
"INT_L_X0Y89/LVB_L4",
"INT_L_X0Y90/LVB_L5",
"INT_L_X0Y91/LVB_L6",
"INT_L_X0Y92/LVB_L7",
"INT_L_X0Y93/LVB_L8",
"INT_L_X0Y94/LVB_L9",
"INT_L_X0Y95/LVB_L10",
"INT_L_X0Y96/LVB_L11",
"INT_L_X0Y97/LVB_L12",
"INT_L_X0Y97/NN6BEG2",
"INT_L_X0Y98/NN6A2",
"INT_L_X0Y99/NN6B2",
"INT_L_X0Y100/NN6C2",
"INT_L_X0Y101/NN6D2",
"INT_L_X0Y102/NN6E2",
"INT_L_X0Y103/NN6END2",
"INT_L_X0Y103/NR1BEG2",
"INT_L_X0Y104/EE2BEG2",
"INT_L_X0Y104/NR1END2",
"INT_R_X1Y104/EE2A2",
"IO_INT_INTERFACE_L_X0Y12/INT_INTERFACE_LOGIC_OUTS_L18",
"IO_INT_INTERFACE_L_X0Y12/INT_INTERFACE_LOGIC_OUTS_L_B18",
"LIOB33_X0Y11/IOB_IBUF0",
"LIOI3_X0Y11/IOI_ILOGIC0_O",
"LIOI3_X0Y11/IOI_LOGIC_OUTS18_1",
"LIOI3_X0Y11/LIOI_I0",
"LIOI3_X0Y11/LIOI_IBUF0",
"LIOI3_X0Y11/LIOI_ILOGIC0_D",
"L_TERM_INT_X2Y13/TERM_INT_LOGIC_OUTS_L_B18",
"VBRK_X9Y109/VBRK_EE2A2"
]
},
{
"name": "din[2]",
"node": "INT_L_X0Y106/EE2BEG2",
"pin": "W16",
"type": "in",
"wire": "VBRK_X9Y111/VBRK_EE2A2",
"wires_outside_roi": [
"BRKH_INT_X0Y49/BRKH_INT_L_LV2",
"BRKH_INT_X0Y99/BRKH_INT_L_LV16",
"CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_5",
"CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_6",
"HCLK_L_X4Y26/HCLK_LV13",
"HCLK_L_X4Y78/HCLK_LV9",
"INT_INTERFACE_R_X1Y106/INT_INTERFACE_EE2A2",
"INT_L_X0Y10/LOGIC_OUTS_L18",
"INT_L_X0Y10/NR1BEG0",
"INT_L_X0Y11/LV_L0",
"INT_L_X0Y11/NR1END0",
"INT_L_X0Y12/LV_L1",
"INT_L_X0Y13/LV_L2",
"INT_L_X0Y14/LV_L3",
"INT_L_X0Y15/LV_L4",
"INT_L_X0Y16/LV_L5",
"INT_L_X0Y17/LV_L6",
"INT_L_X0Y18/LV_L7",
"INT_L_X0Y19/LV_L8",
"INT_L_X0Y20/LV_L9",
"INT_L_X0Y21/LV_L10",
"INT_L_X0Y22/LV_L11",
"INT_L_X0Y23/LV_L12",
"INT_L_X0Y24/LV_L13",
"INT_L_X0Y25/LV_L14",
"INT_L_X0Y26/LV_L15",
"INT_L_X0Y27/LV_L16",
"INT_L_X0Y28/LV_L17",
"INT_L_X0Y29/LV_L0",
"INT_L_X0Y29/LV_L18",
"INT_L_X0Y30/LV_L1",
"INT_L_X0Y31/LV_L2",
"INT_L_X0Y32/LV_L3",
"INT_L_X0Y33/LV_L4",
"INT_L_X0Y34/LV_L5",
"INT_L_X0Y35/LV_L6",
"INT_L_X0Y36/LV_L7",
"INT_L_X0Y37/LV_L8",
"INT_L_X0Y38/LV_L9",
"INT_L_X0Y39/LV_L10",
"INT_L_X0Y40/LV_L11",
"INT_L_X0Y41/LV_L12",
"INT_L_X0Y42/LV_L13",
"INT_L_X0Y43/LV_L14",
"INT_L_X0Y44/LV_L15",
"INT_L_X0Y45/LV_L16",
"INT_L_X0Y46/LV_L17",
"INT_L_X0Y47/LV_L0",
"INT_L_X0Y47/LV_L18",
"INT_L_X0Y48/LV_L1",
"INT_L_X0Y49/LV_L2",
"INT_L_X0Y50/LV_L3",
"INT_L_X0Y51/LV_L4",
"INT_L_X0Y52/LV_L5",
"INT_L_X0Y53/LV_L6",
"INT_L_X0Y54/LV_L7",
"INT_L_X0Y55/LV_L8",
"INT_L_X0Y56/LV_L9",
"INT_L_X0Y57/LV_L10",
"INT_L_X0Y58/LV_L11",
"INT_L_X0Y59/LV_L12",
"INT_L_X0Y60/LV_L13",
"INT_L_X0Y61/LV_L14",
"INT_L_X0Y62/LV_L15",
"INT_L_X0Y63/LV_L16",
"INT_L_X0Y64/LV_L17",
"INT_L_X0Y65/LV_L0",
"INT_L_X0Y65/LV_L18",
"INT_L_X0Y66/LV_L1",
"INT_L_X0Y67/LV_L2",
"INT_L_X0Y68/LV_L3",
"INT_L_X0Y69/LV_L4",
"INT_L_X0Y70/LV_L5",
"INT_L_X0Y71/LV_L6",
"INT_L_X0Y72/LV_L7",
"INT_L_X0Y73/LV_L8",
"INT_L_X0Y74/LV_L9",
"INT_L_X0Y75/LV_L10",
"INT_L_X0Y76/LV_L11",
"INT_L_X0Y77/LV_L12",
"INT_L_X0Y78/LV_L13",
"INT_L_X0Y79/LV_L14",
"INT_L_X0Y80/LV_L15",
"INT_L_X0Y81/LV_L16",
"INT_L_X0Y82/LV_L17",
"INT_L_X0Y83/LV_L0",
"INT_L_X0Y83/LV_L18",
"INT_L_X0Y84/LV_L1",
"INT_L_X0Y85/LV_L2",
"INT_L_X0Y86/LV_L3",
"INT_L_X0Y87/LV_L4",
"INT_L_X0Y88/LV_L5",
"INT_L_X0Y89/LV_L6",
"INT_L_X0Y90/LV_L7",
"INT_L_X0Y91/LV_L8",
"INT_L_X0Y92/LV_L9",
"INT_L_X0Y93/LV_L10",
"INT_L_X0Y94/LV_L11",
"INT_L_X0Y95/LV_L12",
"INT_L_X0Y96/LV_L13",
"INT_L_X0Y97/LV_L14",
"INT_L_X0Y98/LV_L15",
"INT_L_X0Y99/LV_L16",
"INT_L_X0Y100/LV_L17",
"INT_L_X0Y101/LV_L18",
"INT_L_X0Y101/NN6BEG3",
"INT_L_X0Y102/NN6A3",
"INT_L_X0Y103/NN6B3",
"INT_L_X0Y104/NN6C3",
"INT_L_X0Y105/NN6D3",
"INT_L_X0Y106/EE2BEG2",
"INT_L_X0Y106/EL1END2",
"INT_L_X0Y106/NN6E3",
"INT_L_X0Y106/SR1END3",
"INT_L_X0Y106/WL1BEG2",
"INT_L_X0Y107/NN6END3",
"INT_L_X0Y107/SR1BEG3",
"INT_L_X0Y107/SR1END_N3_3",
"INT_R_X1Y106/EE2A2",
"IO_INT_INTERFACE_L_X0Y10/INT_INTERFACE_LOGIC_OUTS_L18",
"IO_INT_INTERFACE_L_X0Y10/INT_INTERFACE_LOGIC_OUTS_L_B18",
"IO_INT_INTERFACE_L_X0Y106/INT_INTERFACE_EL1BEG2",
"IO_INT_INTERFACE_L_X0Y106/INT_INTERFACE_WL1END2",
"LIOB33_X0Y9/IOB_IBUF0",
"LIOI3_X0Y9/IOI_ILOGIC0_O",
"LIOI3_X0Y9/IOI_LOGIC_OUTS18_1",
"LIOI3_X0Y9/LIOI_I0",
"LIOI3_X0Y9/LIOI_IBUF0",
"LIOI3_X0Y9/LIOI_ILOGIC0_D",
"L_TERM_INT_X2Y11/TERM_INT_LOGIC_OUTS_L_B18",
"L_TERM_INT_X2Y111/L_TERM_INT_WL1BEG2",
"VBRK_X9Y111/VBRK_EE2A2"
]
},
{
"name": "din[3]",
"node": "INT_L_X0Y108/EE2BEG2",
"pin": "W17",
"type": "in",
"wire": "VBRK_X9Y113/VBRK_EE2A2",
"wires_outside_roi": [
"BRKH_INT_X0Y49/BRKH_INT_L_LV3",
"BRKH_INT_X0Y99/BRKH_INT_L_LV17",
"CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_7",
"CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_8",
"HCLK_L_X4Y26/HCLK_LV14",
"HCLK_L_X4Y78/HCLK_LV10",
"INT_INTERFACE_R_X1Y108/INT_INTERFACE_EE2A2",
"INT_L_X0Y9/LOGIC_OUTS_L18",
"INT_L_X0Y9/NR1BEG0",
"INT_L_X0Y10/LV_L0",
"INT_L_X0Y10/NR1END0",
"INT_L_X0Y11/LV_L1",
"INT_L_X0Y12/LV_L2",
"INT_L_X0Y13/LV_L3",
"INT_L_X0Y14/LV_L4",
"INT_L_X0Y15/LV_L5",
"INT_L_X0Y16/LV_L6",
"INT_L_X0Y17/LV_L7",
"INT_L_X0Y18/LV_L8",
"INT_L_X0Y19/LV_L9",
"INT_L_X0Y20/LV_L10",
"INT_L_X0Y21/LV_L11",
"INT_L_X0Y22/LV_L12",
"INT_L_X0Y23/LV_L13",
"INT_L_X0Y24/LV_L14",
"INT_L_X0Y25/LV_L15",
"INT_L_X0Y26/LV_L16",
"INT_L_X0Y27/LV_L17",
"INT_L_X0Y28/LV_L0",
"INT_L_X0Y28/LV_L18",
"INT_L_X0Y29/LV_L1",
"INT_L_X0Y30/LV_L2",
"INT_L_X0Y31/LV_L3",
"INT_L_X0Y32/LV_L4",
"INT_L_X0Y33/LV_L5",
"INT_L_X0Y34/LV_L6",
"INT_L_X0Y35/LV_L7",
"INT_L_X0Y36/LV_L8",
"INT_L_X0Y37/LV_L9",
"INT_L_X0Y38/LV_L10",
"INT_L_X0Y39/LV_L11",
"INT_L_X0Y40/LV_L12",
"INT_L_X0Y41/LV_L13",
"INT_L_X0Y42/LV_L14",
"INT_L_X0Y43/LV_L15",
"INT_L_X0Y44/LV_L16",
"INT_L_X0Y45/LV_L17",
"INT_L_X0Y46/LV_L0",
"INT_L_X0Y46/LV_L18",
"INT_L_X0Y47/LV_L1",
"INT_L_X0Y48/LV_L2",
"INT_L_X0Y49/LV_L3",
"INT_L_X0Y50/LV_L4",
"INT_L_X0Y51/LV_L5",
"INT_L_X0Y52/LV_L6",
"INT_L_X0Y53/LV_L7",
"INT_L_X0Y54/LV_L8",
"INT_L_X0Y55/LV_L9",
"INT_L_X0Y56/LV_L10",
"INT_L_X0Y57/LV_L11",
"INT_L_X0Y58/LV_L12",
"INT_L_X0Y59/LV_L13",
"INT_L_X0Y60/LV_L14",
"INT_L_X0Y61/LV_L15",
"INT_L_X0Y62/LV_L16",
"INT_L_X0Y63/LV_L17",
"INT_L_X0Y64/LV_L0",
"INT_L_X0Y64/LV_L18",
"INT_L_X0Y65/LV_L1",
"INT_L_X0Y66/LV_L2",
"INT_L_X0Y67/LV_L3",
"INT_L_X0Y68/LV_L4",
"INT_L_X0Y69/LV_L5",
"INT_L_X0Y70/LV_L6",
"INT_L_X0Y71/LV_L7",
"INT_L_X0Y72/LV_L8",
"INT_L_X0Y73/LV_L9",
"INT_L_X0Y74/LV_L10",
"INT_L_X0Y75/LV_L11",
"INT_L_X0Y76/LV_L12",
"INT_L_X0Y77/LV_L13",
"INT_L_X0Y78/LV_L14",
"INT_L_X0Y79/LV_L15",
"INT_L_X0Y80/LV_L16",
"INT_L_X0Y81/LV_L17",
"INT_L_X0Y82/LV_L0",
"INT_L_X0Y82/LV_L18",
"INT_L_X0Y83/LV_L1",
"INT_L_X0Y84/LV_L2",
"INT_L_X0Y85/LV_L3",
"INT_L_X0Y86/LV_L4",
"INT_L_X0Y87/LV_L5",
"INT_L_X0Y88/LV_L6",
"INT_L_X0Y89/LV_L7",
"INT_L_X0Y90/LV_L8",
"INT_L_X0Y91/LV_L9",
"INT_L_X0Y92/LV_L10",
"INT_L_X0Y93/LV_L11",
"INT_L_X0Y94/LV_L12",
"INT_L_X0Y95/LV_L13",
"INT_L_X0Y96/LV_L14",
"INT_L_X0Y97/LV_L15",
"INT_L_X0Y98/LV_L16",
"INT_L_X0Y99/LV_L17",
"INT_L_X0Y100/LV_L18",
"INT_L_X0Y100/NN6BEG3",
"INT_L_X0Y101/NN6A3",
"INT_L_X0Y102/NN6B3",
"INT_L_X0Y103/NN6C3",
"INT_L_X0Y104/NN6D3",
"INT_L_X0Y105/NN6E3",
"INT_L_X0Y106/NN6END3",
"INT_L_X0Y106/NR1BEG3",
"INT_L_X0Y107/NL1BEG2",
"INT_L_X0Y107/NR1END3",
"INT_L_X0Y108/EE2BEG2",
"INT_L_X0Y108/NL1END2",
"INT_R_X1Y108/EE2A2",
"IO_INT_INTERFACE_L_X0Y9/INT_INTERFACE_LOGIC_OUTS_L18",
"IO_INT_INTERFACE_L_X0Y9/INT_INTERFACE_LOGIC_OUTS_L_B18",
"LIOB33_X0Y9/IOB_IBUF1",
"LIOI3_X0Y9/IOI_ILOGIC1_O",
"LIOI3_X0Y9/IOI_LOGIC_OUTS18_0",
"LIOI3_X0Y9/LIOI_I1",
"LIOI3_X0Y9/LIOI_IBUF1",
"LIOI3_X0Y9/LIOI_ILOGIC1_D",
"L_TERM_INT_X2Y10/TERM_INT_LOGIC_OUTS_L_B18",
"VBRK_X9Y113/VBRK_EE2A2"
]
},
{
"name": "din[4]",
"node": "INT_L_X0Y110/EE2BEG2",
"pin": "W15",
"type": "in",
"wire": "VBRK_X9Y115/VBRK_EE2A2",
"wires_outside_roi": [
"BRKH_INT_X0Y49/BRKH_INT_L_LV5",
"BRKH_INT_X0Y99/BRKH_INT_LVB_L8",
"CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_9",
"CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_10",
"HCLK_L_X4Y26/HCLK_LV16",
"HCLK_L_X4Y78/HCLK_LV12",
"INT_INTERFACE_R_X1Y110/INT_INTERFACE_EE2A2",
"INT_L_X0Y7/LOGIC_OUTS_L18",
"INT_L_X0Y7/NR1BEG0",
"INT_L_X0Y8/LV_L0",
"INT_L_X0Y8/NR1END0",
"INT_L_X0Y9/LV_L1",
"INT_L_X0Y10/LV_L2",
"INT_L_X0Y11/LV_L3",
"INT_L_X0Y12/LV_L4",
"INT_L_X0Y13/LV_L5",
"INT_L_X0Y14/LV_L6",
"INT_L_X0Y15/LV_L7",
"INT_L_X0Y16/LV_L8",
"INT_L_X0Y17/LV_L9",
"INT_L_X0Y18/LV_L10",
"INT_L_X0Y19/LV_L11",
"INT_L_X0Y20/LV_L12",
"INT_L_X0Y21/LV_L13",
"INT_L_X0Y22/LV_L14",
"INT_L_X0Y23/LV_L15",
"INT_L_X0Y24/LV_L16",
"INT_L_X0Y25/LV_L17",
"INT_L_X0Y26/LV_L0",
"INT_L_X0Y26/LV_L18",
"INT_L_X0Y27/LV_L1",
"INT_L_X0Y28/LV_L2",
"INT_L_X0Y29/LV_L3",
"INT_L_X0Y30/LV_L4",
"INT_L_X0Y31/LV_L5",
"INT_L_X0Y32/LV_L6",
"INT_L_X0Y33/LV_L7",
"INT_L_X0Y34/LV_L8",
"INT_L_X0Y35/LV_L9",
"INT_L_X0Y36/LV_L10",
"INT_L_X0Y37/LV_L11",
"INT_L_X0Y38/LV_L12",
"INT_L_X0Y39/LV_L13",
"INT_L_X0Y40/LV_L14",
"INT_L_X0Y41/LV_L15",
"INT_L_X0Y42/LV_L16",
"INT_L_X0Y43/LV_L17",
"INT_L_X0Y44/LV_L0",
"INT_L_X0Y44/LV_L18",
"INT_L_X0Y45/LV_L1",
"INT_L_X0Y46/LV_L2",
"INT_L_X0Y47/LV_L3",
"INT_L_X0Y48/LV_L4",
"INT_L_X0Y49/LV_L5",
"INT_L_X0Y50/LV_L6",
"INT_L_X0Y51/LV_L7",
"INT_L_X0Y52/LV_L8",
"INT_L_X0Y53/LV_L9",
"INT_L_X0Y54/LV_L10",
"INT_L_X0Y55/LV_L11",
"INT_L_X0Y56/LV_L12",
"INT_L_X0Y57/LV_L13",
"INT_L_X0Y58/LV_L14",
"INT_L_X0Y59/LV_L15",
"INT_L_X0Y60/LV_L16",
"INT_L_X0Y61/LV_L17",
"INT_L_X0Y62/LV_L0",
"INT_L_X0Y62/LV_L18",
"INT_L_X0Y63/LV_L1",
"INT_L_X0Y64/LV_L2",
"INT_L_X0Y65/LV_L3",
"INT_L_X0Y66/LV_L4",
"INT_L_X0Y67/LV_L5",
"INT_L_X0Y68/LV_L6",
"INT_L_X0Y69/LV_L7",
"INT_L_X0Y70/LV_L8",
"INT_L_X0Y71/LV_L9",
"INT_L_X0Y72/LV_L10",
"INT_L_X0Y73/LV_L11",
"INT_L_X0Y74/LV_L12",
"INT_L_X0Y75/LV_L13",
"INT_L_X0Y76/LV_L14",
"INT_L_X0Y77/LV_L15",
"INT_L_X0Y78/LV_L16",
"INT_L_X0Y79/LV_L17",
"INT_L_X0Y80/LVB_L0",
"INT_L_X0Y80/LV_L18",
"INT_L_X0Y81/LVB_L1",
"INT_L_X0Y82/LVB_L2",
"INT_L_X0Y83/LVB_L3",
"INT_L_X0Y84/LVB_L4",
"INT_L_X0Y85/LVB_L5",
"INT_L_X0Y86/LVB_L6",
"INT_L_X0Y87/LVB_L7",
"INT_L_X0Y88/LVB_L8",
"INT_L_X0Y89/LVB_L9",
"INT_L_X0Y90/LVB_L10",
"INT_L_X0Y91/LVB_L11",
"INT_L_X0Y92/LVB_L0",
"INT_L_X0Y92/LVB_L12",
"INT_L_X0Y93/LVB_L1",
"INT_L_X0Y94/LVB_L2",
"INT_L_X0Y95/LVB_L3",
"INT_L_X0Y96/LVB_L4",
"INT_L_X0Y97/LVB_L5",
"INT_L_X0Y98/LVB_L6",
"INT_L_X0Y99/LVB_L7",
"INT_L_X0Y100/LVB_L8",
"INT_L_X0Y101/LVB_L9",
"INT_L_X0Y102/LVB_L10",
"INT_L_X0Y103/LVB_L11",
"INT_L_X0Y104/LVB_L12",
"INT_L_X0Y104/NN6BEG2",
"INT_L_X0Y105/NN6A2",
"INT_L_X0Y106/NN6B2",
"INT_L_X0Y107/NN6C2",
"INT_L_X0Y108/NN6D2",
"INT_L_X0Y109/NN6E2",
"INT_L_X0Y110/EE2BEG2",
"INT_L_X0Y110/NN6END2",
"INT_R_X1Y110/EE2A2",
"IO_INT_INTERFACE_L_X0Y7/INT_INTERFACE_LOGIC_OUTS_L18",
"IO_INT_INTERFACE_L_X0Y7/INT_INTERFACE_LOGIC_OUTS_L_B18",
"LIOB33_X0Y7/IOB_IBUF1",
"LIOI3_TBYTESRC_X0Y7/IOI_ILOGIC1_O",
"LIOI3_TBYTESRC_X0Y7/IOI_LOGIC_OUTS18_0",
"LIOI3_TBYTESRC_X0Y7/LIOI_I1",
"LIOI3_TBYTESRC_X0Y7/LIOI_IBUF1",
"LIOI3_TBYTESRC_X0Y7/LIOI_ILOGIC1_D",
"L_TERM_INT_X2Y8/TERM_INT_LOGIC_OUTS_L_B18",
"VBRK_X9Y115/VBRK_EE2A2"
]
},
{
"name": "din[5]",
"node": "INT_L_X0Y112/EE2BEG2",
"pin": "V15",
"type": "in",
"wire": "VBRK_X9Y117/VBRK_EE2A2",
"wires_outside_roi": [
"BRKH_INT_X0Y49/BRKH_INT_L_LV4",
"BRKH_INT_X0Y99/BRKH_INT_NN6BEG3",
"CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_11",
"CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_12",
"HCLK_L_X4Y26/HCLK_LV15",
"HCLK_L_X4Y78/HCLK_LV11",
"INT_INTERFACE_R_X1Y112/INT_INTERFACE_EE2A2",
"INT_L_X0Y8/LOGIC_OUTS_L18",
"INT_L_X0Y8/NR1BEG0",
"INT_L_X0Y9/LV_L0",
"INT_L_X0Y9/NR1END0",
"INT_L_X0Y10/LV_L1",
"INT_L_X0Y11/LV_L2",
"INT_L_X0Y12/LV_L3",
"INT_L_X0Y13/LV_L4",
"INT_L_X0Y14/LV_L5",
"INT_L_X0Y15/LV_L6",
"INT_L_X0Y16/LV_L7",
"INT_L_X0Y17/LV_L8",
"INT_L_X0Y18/LV_L9",
"INT_L_X0Y19/LV_L10",
"INT_L_X0Y20/LV_L11",
"INT_L_X0Y21/LV_L12",
"INT_L_X0Y22/LV_L13",
"INT_L_X0Y23/LV_L14",
"INT_L_X0Y24/LV_L15",
"INT_L_X0Y25/LV_L16",
"INT_L_X0Y26/LV_L17",
"INT_L_X0Y27/LV_L0",
"INT_L_X0Y27/LV_L18",
"INT_L_X0Y28/LV_L1",
"INT_L_X0Y29/LV_L2",
"INT_L_X0Y30/LV_L3",
"INT_L_X0Y31/LV_L4",
"INT_L_X0Y32/LV_L5",
"INT_L_X0Y33/LV_L6",
"INT_L_X0Y34/LV_L7",
"INT_L_X0Y35/LV_L8",
"INT_L_X0Y36/LV_L9",
"INT_L_X0Y37/LV_L10",
"INT_L_X0Y38/LV_L11",
"INT_L_X0Y39/LV_L12",
"INT_L_X0Y40/LV_L13",
"INT_L_X0Y41/LV_L14",
"INT_L_X0Y42/LV_L15",
"INT_L_X0Y43/LV_L16",
"INT_L_X0Y44/LV_L17",
"INT_L_X0Y45/LV_L0",
"INT_L_X0Y45/LV_L18",
"INT_L_X0Y46/LV_L1",
"INT_L_X0Y47/LV_L2",
"INT_L_X0Y48/LV_L3",
"INT_L_X0Y49/LV_L4",
"INT_L_X0Y50/LV_L5",
"INT_L_X0Y51/LV_L6",
"INT_L_X0Y52/LV_L7",
"INT_L_X0Y53/LV_L8",
"INT_L_X0Y54/LV_L9",
"INT_L_X0Y55/LV_L10",
"INT_L_X0Y56/LV_L11",
"INT_L_X0Y57/LV_L12",
"INT_L_X0Y58/LV_L13",
"INT_L_X0Y59/LV_L14",
"INT_L_X0Y60/LV_L15",
"INT_L_X0Y61/LV_L16",
"INT_L_X0Y62/LV_L17",
"INT_L_X0Y63/LV_L0",
"INT_L_X0Y63/LV_L18",
"INT_L_X0Y64/LV_L1",
"INT_L_X0Y65/LV_L2",
"INT_L_X0Y66/LV_L3",
"INT_L_X0Y67/LV_L4",
"INT_L_X0Y68/LV_L5",
"INT_L_X0Y69/LV_L6",
"INT_L_X0Y70/LV_L7",
"INT_L_X0Y71/LV_L8",
"INT_L_X0Y72/LV_L9",
"INT_L_X0Y73/LV_L10",
"INT_L_X0Y74/LV_L11",
"INT_L_X0Y75/LV_L12",
"INT_L_X0Y76/LV_L13",
"INT_L_X0Y77/LV_L14",
"INT_L_X0Y78/LV_L15",
"INT_L_X0Y79/LV_L16",
"INT_L_X0Y80/LV_L17",
"INT_L_X0Y81/LV_L0",
"INT_L_X0Y81/LV_L18",
"INT_L_X0Y82/LV_L1",
"INT_L_X0Y83/LV_L2",
"INT_L_X0Y84/LV_L3",
"INT_L_X0Y85/LV_L4",
"INT_L_X0Y86/LV_L5",
"INT_L_X0Y87/LV_L6",
"INT_L_X0Y88/LV_L7",
"INT_L_X0Y89/LV_L8",
"INT_L_X0Y90/LV_L9",
"INT_L_X0Y91/LV_L10",
"INT_L_X0Y92/LV_L11",
"INT_L_X0Y93/LV_L12",
"INT_L_X0Y94/LV_L13",
"INT_L_X0Y95/LV_L14",
"INT_L_X0Y96/LV_L15",
"INT_L_X0Y97/LV_L16",
"INT_L_X0Y98/LV_L17",
"INT_L_X0Y99/LV_L18",
"INT_L_X0Y99/NN6BEG3",
"INT_L_X0Y100/NN6A3",
"INT_L_X0Y101/NN6B3",
"INT_L_X0Y102/NN6C3",
"INT_L_X0Y103/NN6D3",
"INT_L_X0Y104/NN6E3",
"INT_L_X0Y105/NN6BEG3",
"INT_L_X0Y105/NN6END3",
"INT_L_X0Y106/NN6A3",
"INT_L_X0Y107/NN6B3",
"INT_L_X0Y108/NN6C3",
"INT_L_X0Y109/NN6D3",
"INT_L_X0Y110/NN6E3",
"INT_L_X0Y111/NL1BEG2",
"INT_L_X0Y111/NN6END3",
"INT_L_X0Y112/EE2BEG2",
"INT_L_X0Y112/NL1END2",
"INT_R_X1Y112/EE2A2",
"IO_INT_INTERFACE_L_X0Y8/INT_INTERFACE_LOGIC_OUTS_L18",
"IO_INT_INTERFACE_L_X0Y8/INT_INTERFACE_LOGIC_OUTS_L_B18",
"LIOB33_X0Y7/IOB_IBUF0",
"LIOI3_TBYTESRC_X0Y7/IOI_ILOGIC0_O",
"LIOI3_TBYTESRC_X0Y7/IOI_LOGIC_OUTS18_1",
"LIOI3_TBYTESRC_X0Y7/LIOI_I0",
"LIOI3_TBYTESRC_X0Y7/LIOI_IBUF0",
"LIOI3_TBYTESRC_X0Y7/LIOI_ILOGIC0_D",
"L_TERM_INT_X2Y9/TERM_INT_LOGIC_OUTS_L_B18",
"VBRK_X9Y117/VBRK_EE2A2"
]
},
{
"name": "din[6]",
"node": "INT_L_X0Y114/EE2BEG2",
"pin": "W14",
"type": "in",
"wire": "VBRK_X9Y119/VBRK_EE2A2",
"wires_outside_roi": [
"BRKH_INT_X0Y49/BRKH_INT_L_LV7",
"BRKH_INT_X0Y99/BRKH_INT_LVB_L4",
"CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_1",
"CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_14",
"HCLK_L_X4Y26/HCLK_LV0",
"HCLK_L_X4Y78/HCLK_LV14",
"INT_INTERFACE_R_X1Y114/INT_INTERFACE_EE2A2",
"INT_L_X0Y5/LOGIC_OUTS_L18",
"INT_L_X0Y5/NR1BEG0",
"INT_L_X0Y6/LV_L0",
"INT_L_X0Y6/NR1END0",
"INT_L_X0Y7/LV_L1",
"INT_L_X0Y8/LV_L2",
"INT_L_X0Y9/LV_L3",
"INT_L_X0Y10/LV_L4",
"INT_L_X0Y11/LV_L5",
"INT_L_X0Y12/LV_L6",
"INT_L_X0Y13/LV_L7",
"INT_L_X0Y14/LV_L8",
"INT_L_X0Y15/LV_L9",
"INT_L_X0Y16/LV_L10",
"INT_L_X0Y17/LV_L11",
"INT_L_X0Y18/LV_L12",
"INT_L_X0Y19/LV_L13",
"INT_L_X0Y20/LV_L14",
"INT_L_X0Y21/LV_L15",
"INT_L_X0Y22/LV_L16",
"INT_L_X0Y23/LV_L17",
"INT_L_X0Y24/LV_L0",
"INT_L_X0Y24/LV_L18",
"INT_L_X0Y25/LV_L1",
"INT_L_X0Y26/LV_L2",
"INT_L_X0Y27/LV_L3",
"INT_L_X0Y28/LV_L4",
"INT_L_X0Y29/LV_L5",
"INT_L_X0Y30/LV_L6",
"INT_L_X0Y31/LV_L7",
"INT_L_X0Y32/LV_L8",
"INT_L_X0Y33/LV_L9",
"INT_L_X0Y34/LV_L10",
"INT_L_X0Y35/LV_L11",
"INT_L_X0Y36/LV_L12",
"INT_L_X0Y37/LV_L13",
"INT_L_X0Y38/LV_L14",
"INT_L_X0Y39/LV_L15",
"INT_L_X0Y40/LV_L16",
"INT_L_X0Y41/LV_L17",
"INT_L_X0Y42/LV_L0",
"INT_L_X0Y42/LV_L18",
"INT_L_X0Y43/LV_L1",
"INT_L_X0Y44/LV_L2",
"INT_L_X0Y45/LV_L3",
"INT_L_X0Y46/LV_L4",
"INT_L_X0Y47/LV_L5",
"INT_L_X0Y48/LV_L6",
"INT_L_X0Y49/LV_L7",
"INT_L_X0Y50/LV_L8",
"INT_L_X0Y51/LV_L9",
"INT_L_X0Y52/LV_L10",
"INT_L_X0Y53/LV_L11",
"INT_L_X0Y54/LV_L12",
"INT_L_X0Y55/LV_L13",
"INT_L_X0Y56/LV_L14",
"INT_L_X0Y57/LV_L15",
"INT_L_X0Y58/LV_L16",
"INT_L_X0Y59/LV_L17",
"INT_L_X0Y60/LV_L0",
"INT_L_X0Y60/LV_L18",
"INT_L_X0Y61/LV_L1",
"INT_L_X0Y62/LV_L2",
"INT_L_X0Y63/LV_L3",
"INT_L_X0Y64/LV_L4",
"INT_L_X0Y65/LV_L5",
"INT_L_X0Y66/LV_L6",
"INT_L_X0Y67/LV_L7",
"INT_L_X0Y68/LV_L8",
"INT_L_X0Y69/LV_L9",
"INT_L_X0Y70/LV_L10",
"INT_L_X0Y71/LV_L11",
"INT_L_X0Y72/LV_L12",
"INT_L_X0Y73/LV_L13",
"INT_L_X0Y74/LV_L14",
"INT_L_X0Y75/LV_L15",
"INT_L_X0Y76/LV_L16",
"INT_L_X0Y77/LV_L17",
"INT_L_X0Y78/LV_L0",
"INT_L_X0Y78/LV_L18",
"INT_L_X0Y79/LV_L1",
"INT_L_X0Y80/LV_L2",
"INT_L_X0Y81/LV_L3",
"INT_L_X0Y82/LV_L4",
"INT_L_X0Y83/LV_L5",
"INT_L_X0Y84/LV_L6",
"INT_L_X0Y85/LV_L7",
"INT_L_X0Y86/LV_L8",
"INT_L_X0Y87/LV_L9",
"INT_L_X0Y88/LV_L10",
"INT_L_X0Y89/LV_L11",
"INT_L_X0Y90/LV_L12",
"INT_L_X0Y91/LV_L13",
"INT_L_X0Y92/LV_L14",
"INT_L_X0Y93/LV_L15",
"INT_L_X0Y94/LV_L16",
"INT_L_X0Y95/LV_L17",
"INT_L_X0Y96/LVB_L0",
"INT_L_X0Y96/LV_L18",
"INT_L_X0Y97/LVB_L1",
"INT_L_X0Y98/LVB_L2",
"INT_L_X0Y99/LVB_L3",
"INT_L_X0Y100/LVB_L4",
"INT_L_X0Y101/LVB_L5",
"INT_L_X0Y102/LVB_L6",
"INT_L_X0Y103/LVB_L7",
"INT_L_X0Y104/LVB_L8",
"INT_L_X0Y105/LVB_L9",
"INT_L_X0Y106/LVB_L10",
"INT_L_X0Y107/LVB_L11",
"INT_L_X0Y108/LVB_L12",
"INT_L_X0Y108/NN6BEG2",
"INT_L_X0Y109/NN6A2",
"INT_L_X0Y110/NN6B2",
"INT_L_X0Y111/NN6C2",
"INT_L_X0Y112/NN6D2",
"INT_L_X0Y113/NN6E2",
"INT_L_X0Y114/EE2BEG2",
"INT_L_X0Y114/NN6END2",
"INT_R_X1Y114/EE2A2",
"IO_INT_INTERFACE_L_X0Y5/INT_INTERFACE_LOGIC_OUTS_L18",
"IO_INT_INTERFACE_L_X0Y5/INT_INTERFACE_LOGIC_OUTS_L_B18",
"LIOB33_X0Y5/IOB_IBUF1",
"LIOI3_X0Y5/IOI_ILOGIC1_O",
"LIOI3_X0Y5/IOI_LOGIC_OUTS18_0",
"LIOI3_X0Y5/LIOI_I1",
"LIOI3_X0Y5/LIOI_IBUF1",
"LIOI3_X0Y5/LIOI_ILOGIC1_D",
"L_TERM_INT_X2Y6/TERM_INT_LOGIC_OUTS_L_B18",
"VBRK_X9Y119/VBRK_EE2A2"
]
},
{
"name": "din[7]",
"node": "INT_L_X0Y116/EE2BEG2",
"pin": "W13",
"type": "in",
"wire": "VBRK_X9Y121/VBRK_EE2A2",
"wires_outside_roi": [
"BRKH_INT_X0Y49/BRKH_INT_L_LV6",
"BRKH_INT_X0Y99/BRKH_INT_LVB_L3",
"CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_3",
"CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_EE2A2_0",
"HCLK_L_X4Y26/HCLK_LV17",
"HCLK_L_X4Y78/HCLK_LV13",
"INT_INTERFACE_R_X1Y116/INT_INTERFACE_EE2A2",
"INT_L_X0Y6/LOGIC_OUTS_L18",
"INT_L_X0Y6/NR1BEG0",
"INT_L_X0Y7/LV_L0",
"INT_L_X0Y7/NR1END0",
"INT_L_X0Y8/LV_L1",
"INT_L_X0Y9/LV_L2",
"INT_L_X0Y10/LV_L3",
"INT_L_X0Y11/LV_L4",
"INT_L_X0Y12/LV_L5",