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segbits_bram_l.origin_info.db
456 lines (456 loc) · 34.8 KB
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segbits_bram_l.origin_info.db
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BRAM_L.BRAM_ADDRARDADDRL0.BRAM_CASCINBOT_ADDRARDADDRU0 origin:060-bram-cascades !26_33 26_32 26_35
BRAM_L.BRAM_ADDRARDADDRL0.BRAM_CASCINTOP_ADDRARDADDRU0 origin:060-bram-cascades !26_35 26_32 26_33
BRAM_L.BRAM_ADDRARDADDRL0.BRAM_IMUX_ADDRARDADDRL0 origin:060-bram-cascades !26_32 !26_33 !26_35
BRAM_L.BRAM_ADDRARDADDRL1.BRAM_CASCINBOT_ADDRARDADDRU1 origin:060-bram-cascades !26_49 26_48 26_51
BRAM_L.BRAM_ADDRARDADDRL1.BRAM_CASCINTOP_ADDRARDADDRU1 origin:060-bram-cascades !26_51 26_48 26_49
BRAM_L.BRAM_ADDRARDADDRL1.BRAM_IMUX_ADDRARDADDRL1 origin:060-bram-cascades !26_48 !26_49 !26_51
BRAM_L.BRAM_ADDRARDADDRL2.BRAM_CASCINBOT_ADDRARDADDRU2 origin:060-bram-cascades !26_65 26_64 26_67
BRAM_L.BRAM_ADDRARDADDRL2.BRAM_CASCINTOP_ADDRARDADDRU2 origin:060-bram-cascades !26_67 26_64 26_65
BRAM_L.BRAM_ADDRARDADDRL2.BRAM_IMUX_ADDRARDADDRL2 origin:060-bram-cascades !26_64 !26_65 !26_67
BRAM_L.BRAM_ADDRARDADDRL3.BRAM_CASCINBOT_ADDRARDADDRU3 origin:060-bram-cascades !26_193 26_192 26_195
BRAM_L.BRAM_ADDRARDADDRL3.BRAM_CASCINTOP_ADDRARDADDRU3 origin:060-bram-cascades !26_195 26_192 26_193
BRAM_L.BRAM_ADDRARDADDRL3.BRAM_IMUX_ADDRARDADDRL3 origin:060-bram-cascades !26_192 !26_193 !26_195
BRAM_L.BRAM_ADDRARDADDRL4.BRAM_CASCINBOT_ADDRARDADDRU4 origin:060-bram-cascades !26_97 26_96 26_99
BRAM_L.BRAM_ADDRARDADDRL4.BRAM_CASCINTOP_ADDRARDADDRU4 origin:060-bram-cascades !26_99 26_96 26_97
BRAM_L.BRAM_ADDRARDADDRL4.BRAM_IMUX_ADDRARDADDRL4 origin:060-bram-cascades !26_96 !26_97 !26_99
BRAM_L.BRAM_ADDRARDADDRL5.BRAM_CASCINBOT_ADDRARDADDRU5 origin:060-bram-cascades !26_225 26_224 26_227
BRAM_L.BRAM_ADDRARDADDRL5.BRAM_CASCINTOP_ADDRARDADDRU5 origin:060-bram-cascades !26_227 26_224 26_225
BRAM_L.BRAM_ADDRARDADDRL5.BRAM_IMUX_ADDRARDADDRL5 origin:060-bram-cascades !26_224 !26_225 !26_227
BRAM_L.BRAM_ADDRARDADDRL6.BRAM_CASCINBOT_ADDRARDADDRU6 origin:060-bram-cascades !26_161 26_160 26_163
BRAM_L.BRAM_ADDRARDADDRL6.BRAM_CASCINTOP_ADDRARDADDRU6 origin:060-bram-cascades !26_163 26_160 26_161
BRAM_L.BRAM_ADDRARDADDRL6.BRAM_IMUX_ADDRARDADDRL6 origin:060-bram-cascades !26_160 !26_161 !26_163
BRAM_L.BRAM_ADDRARDADDRL7.BRAM_CASCINBOT_ADDRARDADDRU7 origin:060-bram-cascades !26_177 26_176 26_179
BRAM_L.BRAM_ADDRARDADDRL7.BRAM_CASCINTOP_ADDRARDADDRU7 origin:060-bram-cascades !26_179 26_176 26_177
BRAM_L.BRAM_ADDRARDADDRL7.BRAM_IMUX_ADDRARDADDRL7 origin:060-bram-cascades !26_176 !26_177 !26_179
BRAM_L.BRAM_ADDRARDADDRL8.BRAM_CASCINBOT_ADDRARDADDRU8 origin:060-bram-cascades !26_81 26_80 26_83
BRAM_L.BRAM_ADDRARDADDRL8.BRAM_CASCINTOP_ADDRARDADDRU8 origin:060-bram-cascades !26_83 26_80 26_81
BRAM_L.BRAM_ADDRARDADDRL8.BRAM_IMUX_ADDRARDADDRL8 origin:060-bram-cascades !26_80 !26_81 !26_83
BRAM_L.BRAM_ADDRARDADDRL9.BRAM_CASCINBOT_ADDRARDADDRU9 origin:060-bram-cascades !26_209 26_208 26_211
BRAM_L.BRAM_ADDRARDADDRL9.BRAM_CASCINTOP_ADDRARDADDRU9 origin:060-bram-cascades !26_211 26_208 26_209
BRAM_L.BRAM_ADDRARDADDRL9.BRAM_IMUX_ADDRARDADDRL9 origin:060-bram-cascades !26_208 !26_209 !26_211
BRAM_L.BRAM_ADDRARDADDRL10.BRAM_CASCINBOT_ADDRARDADDRU10 origin:060-bram-cascades !26_145 26_144 26_147
BRAM_L.BRAM_ADDRARDADDRL10.BRAM_CASCINTOP_ADDRARDADDRU10 origin:060-bram-cascades !26_147 26_144 26_145
BRAM_L.BRAM_ADDRARDADDRL10.BRAM_IMUX_ADDRARDADDRL10 origin:060-bram-cascades !26_144 !26_145 !26_147
BRAM_L.BRAM_ADDRARDADDRL11.BRAM_CASCINBOT_ADDRARDADDRU11 origin:060-bram-cascades !26_113 26_112 26_115
BRAM_L.BRAM_ADDRARDADDRL11.BRAM_CASCINTOP_ADDRARDADDRU11 origin:060-bram-cascades !26_115 26_112 26_113
BRAM_L.BRAM_ADDRARDADDRL11.BRAM_IMUX_ADDRARDADDRL11 origin:060-bram-cascades !26_112 !26_113 !26_115
BRAM_L.BRAM_ADDRARDADDRL12.BRAM_CASCINBOT_ADDRARDADDRU12 origin:060-bram-cascades !26_241 26_240 26_243
BRAM_L.BRAM_ADDRARDADDRL12.BRAM_CASCINTOP_ADDRARDADDRU12 origin:060-bram-cascades !26_243 26_240 26_241
BRAM_L.BRAM_ADDRARDADDRL12.BRAM_IMUX_ADDRARDADDRL12 origin:060-bram-cascades !26_240 !26_241 !26_243
BRAM_L.BRAM_ADDRARDADDRL13.BRAM_CASCINBOT_ADDRARDADDRU13 origin:060-bram-cascades !26_129 26_128 26_131
BRAM_L.BRAM_ADDRARDADDRL13.BRAM_CASCINTOP_ADDRARDADDRU13 origin:060-bram-cascades !26_131 26_128 26_129
BRAM_L.BRAM_ADDRARDADDRL13.BRAM_IMUX_ADDRARDADDRL13 origin:060-bram-cascades !26_128 !26_129 !26_131
BRAM_L.BRAM_ADDRARDADDRL14.BRAM_CASCINBOT_ADDRARDADDRU14 origin:060-bram-cascades !26_257 26_256 26_259
BRAM_L.BRAM_ADDRARDADDRL14.BRAM_CASCINTOP_ADDRARDADDRU14 origin:060-bram-cascades !26_259 26_256 26_257
BRAM_L.BRAM_ADDRARDADDRL14.BRAM_IMUX_ADDRARDADDRL14 origin:060-bram-cascades !26_256 !26_257 !26_259
BRAM_L.BRAM_ADDRARDADDRU0.BRAM_CASCINBOT_ADDRARDADDRU0 origin:060-bram-cascades !26_38 26_37 26_39
BRAM_L.BRAM_ADDRARDADDRU0.BRAM_CASCINTOP_ADDRARDADDRU0 origin:060-bram-cascades !26_37 26_38 26_39
BRAM_L.BRAM_ADDRARDADDRU0.BRAM_IMUX_ADDRARDADDRU0 origin:060-bram-cascades !26_37 !26_38 !26_39
BRAM_L.BRAM_ADDRARDADDRU1.BRAM_CASCINBOT_ADDRARDADDRU1 origin:060-bram-cascades !26_54 26_53 26_55
BRAM_L.BRAM_ADDRARDADDRU1.BRAM_CASCINTOP_ADDRARDADDRU1 origin:060-bram-cascades !26_53 26_54 26_55
BRAM_L.BRAM_ADDRARDADDRU1.BRAM_IMUX_ADDRARDADDRU1 origin:060-bram-cascades !26_53 !26_54 !26_55
BRAM_L.BRAM_ADDRARDADDRU2.BRAM_CASCINBOT_ADDRARDADDRU2 origin:060-bram-cascades !26_70 26_69 26_71
BRAM_L.BRAM_ADDRARDADDRU2.BRAM_CASCINTOP_ADDRARDADDRU2 origin:060-bram-cascades !26_69 26_70 26_71
BRAM_L.BRAM_ADDRARDADDRU2.BRAM_IMUX_ADDRARDADDRU2 origin:060-bram-cascades !26_69 !26_70 !26_71
BRAM_L.BRAM_ADDRARDADDRU3.BRAM_CASCINBOT_ADDRARDADDRU3 origin:060-bram-cascades !26_198 26_197 26_199
BRAM_L.BRAM_ADDRARDADDRU3.BRAM_CASCINTOP_ADDRARDADDRU3 origin:060-bram-cascades !26_197 26_198 26_199
BRAM_L.BRAM_ADDRARDADDRU3.BRAM_IMUX_ADDRARDADDRU3 origin:060-bram-cascades !26_197 !26_198 !26_199
BRAM_L.BRAM_ADDRARDADDRU4.BRAM_CASCINBOT_ADDRARDADDRU4 origin:060-bram-cascades !26_102 26_101 26_103
BRAM_L.BRAM_ADDRARDADDRU4.BRAM_CASCINTOP_ADDRARDADDRU4 origin:060-bram-cascades !26_101 26_102 26_103
BRAM_L.BRAM_ADDRARDADDRU4.BRAM_IMUX_ADDRARDADDRU4 origin:060-bram-cascades !26_101 !26_102 !26_103
BRAM_L.BRAM_ADDRARDADDRU5.BRAM_CASCINBOT_ADDRARDADDRU5 origin:060-bram-cascades !26_230 26_229 26_231
BRAM_L.BRAM_ADDRARDADDRU5.BRAM_CASCINTOP_ADDRARDADDRU5 origin:060-bram-cascades !26_229 26_230 26_231
BRAM_L.BRAM_ADDRARDADDRU5.BRAM_IMUX_ADDRARDADDRU5 origin:060-bram-cascades !26_229 !26_230 !26_231
BRAM_L.BRAM_ADDRARDADDRU6.BRAM_CASCINBOT_ADDRARDADDRU6 origin:060-bram-cascades !26_166 26_165 26_167
BRAM_L.BRAM_ADDRARDADDRU6.BRAM_CASCINTOP_ADDRARDADDRU6 origin:060-bram-cascades !26_165 26_166 26_167
BRAM_L.BRAM_ADDRARDADDRU6.BRAM_IMUX_ADDRARDADDRU6 origin:060-bram-cascades !26_165 !26_166 !26_167
BRAM_L.BRAM_ADDRARDADDRU7.BRAM_CASCINBOT_ADDRARDADDRU7 origin:060-bram-cascades !26_182 26_181 26_183
BRAM_L.BRAM_ADDRARDADDRU7.BRAM_CASCINTOP_ADDRARDADDRU7 origin:060-bram-cascades !26_181 26_182 26_183
BRAM_L.BRAM_ADDRARDADDRU7.BRAM_IMUX_ADDRARDADDRU7 origin:060-bram-cascades !26_181 !26_182 !26_183
BRAM_L.BRAM_ADDRARDADDRU8.BRAM_CASCINBOT_ADDRARDADDRU8 origin:060-bram-cascades !26_86 26_85 26_87
BRAM_L.BRAM_ADDRARDADDRU8.BRAM_CASCINTOP_ADDRARDADDRU8 origin:060-bram-cascades !26_85 26_86 26_87
BRAM_L.BRAM_ADDRARDADDRU8.BRAM_IMUX_ADDRARDADDRU8 origin:060-bram-cascades !26_85 !26_86 !26_87
BRAM_L.BRAM_ADDRARDADDRU9.BRAM_CASCINBOT_ADDRARDADDRU9 origin:060-bram-cascades !26_214 26_213 26_215
BRAM_L.BRAM_ADDRARDADDRU9.BRAM_CASCINTOP_ADDRARDADDRU9 origin:060-bram-cascades !26_213 26_214 26_215
BRAM_L.BRAM_ADDRARDADDRU9.BRAM_IMUX_ADDRARDADDRU9 origin:060-bram-cascades !26_213 !26_214 !26_215
BRAM_L.BRAM_ADDRARDADDRU10.BRAM_CASCINBOT_ADDRARDADDRU10 origin:060-bram-cascades !26_150 26_149 26_151
BRAM_L.BRAM_ADDRARDADDRU10.BRAM_CASCINTOP_ADDRARDADDRU10 origin:060-bram-cascades !26_149 26_150 26_151
BRAM_L.BRAM_ADDRARDADDRU10.BRAM_IMUX_ADDRARDADDRU10 origin:060-bram-cascades !26_149 !26_150 !26_151
BRAM_L.BRAM_ADDRARDADDRU11.BRAM_CASCINBOT_ADDRARDADDRU11 origin:060-bram-cascades !26_118 26_117 26_119
BRAM_L.BRAM_ADDRARDADDRU11.BRAM_CASCINTOP_ADDRARDADDRU11 origin:060-bram-cascades !26_117 26_118 26_119
BRAM_L.BRAM_ADDRARDADDRU11.BRAM_IMUX_ADDRARDADDRU11 origin:060-bram-cascades !26_117 !26_118 !26_119
BRAM_L.BRAM_ADDRARDADDRU12.BRAM_CASCINBOT_ADDRARDADDRU12 origin:060-bram-cascades !26_246 26_245 26_247
BRAM_L.BRAM_ADDRARDADDRU12.BRAM_CASCINTOP_ADDRARDADDRU12 origin:060-bram-cascades !26_245 26_246 26_247
BRAM_L.BRAM_ADDRARDADDRU12.BRAM_IMUX_ADDRARDADDRU12 origin:060-bram-cascades !26_245 !26_246 !26_247
BRAM_L.BRAM_ADDRARDADDRU13.BRAM_CASCINBOT_ADDRARDADDRU13 origin:060-bram-cascades !26_134 26_133 26_135
BRAM_L.BRAM_ADDRARDADDRU13.BRAM_CASCINTOP_ADDRARDADDRU13 origin:060-bram-cascades !26_133 26_134 26_135
BRAM_L.BRAM_ADDRARDADDRU13.BRAM_IMUX_ADDRARDADDRU13 origin:060-bram-cascades !26_133 !26_134 !26_135
BRAM_L.BRAM_ADDRARDADDRU14.BRAM_CASCINBOT_ADDRARDADDRU14 origin:060-bram-cascades !26_262 26_261 26_263
BRAM_L.BRAM_ADDRARDADDRU14.BRAM_CASCINTOP_ADDRARDADDRU14 origin:060-bram-cascades !26_261 26_262 26_263
BRAM_L.BRAM_ADDRARDADDRU14.BRAM_IMUX_ADDRARDADDRU14 origin:060-bram-cascades !26_261 !26_262 !26_263
BRAM_L.BRAM_ADDRBWRADDRL0.BRAM_CASCINBOT_ADDRBWRADDRU0 origin:060-bram-cascades !26_41 26_40 26_43
BRAM_L.BRAM_ADDRBWRADDRL0.BRAM_CASCINTOP_ADDRBWRADDRU0 origin:060-bram-cascades !26_43 26_40 26_41
BRAM_L.BRAM_ADDRBWRADDRL0.BRAM_IMUX_ADDRBWRADDRL0 origin:060-bram-cascades !26_40 !26_41 !26_43
BRAM_L.BRAM_ADDRBWRADDRL1.BRAM_CASCINBOT_ADDRBWRADDRU1 origin:060-bram-cascades !26_57 26_56 26_59
BRAM_L.BRAM_ADDRBWRADDRL1.BRAM_CASCINTOP_ADDRBWRADDRU1 origin:060-bram-cascades !26_59 26_56 26_57
BRAM_L.BRAM_ADDRBWRADDRL1.BRAM_IMUX_ADDRBWRADDRL1 origin:060-bram-cascades !26_56 !26_57 !26_59
BRAM_L.BRAM_ADDRBWRADDRL2.BRAM_CASCINBOT_ADDRBWRADDRU2 origin:060-bram-cascades !26_73 26_72 26_75
BRAM_L.BRAM_ADDRBWRADDRL2.BRAM_CASCINTOP_ADDRBWRADDRU2 origin:060-bram-cascades !26_75 26_72 26_73
BRAM_L.BRAM_ADDRBWRADDRL2.BRAM_IMUX_ADDRBWRADDRL2 origin:060-bram-cascades !26_72 !26_73 !26_75
BRAM_L.BRAM_ADDRBWRADDRL3.BRAM_CASCINBOT_ADDRBWRADDRU3 origin:060-bram-cascades !26_201 26_200 26_203
BRAM_L.BRAM_ADDRBWRADDRL3.BRAM_CASCINTOP_ADDRBWRADDRU3 origin:060-bram-cascades !26_203 26_200 26_201
BRAM_L.BRAM_ADDRBWRADDRL3.BRAM_IMUX_ADDRBWRADDRL3 origin:060-bram-cascades !26_200 !26_201 !26_203
BRAM_L.BRAM_ADDRBWRADDRL4.BRAM_CASCINBOT_ADDRBWRADDRU4 origin:060-bram-cascades !26_105 26_104 26_107
BRAM_L.BRAM_ADDRBWRADDRL4.BRAM_CASCINTOP_ADDRBWRADDRU4 origin:060-bram-cascades !26_107 26_104 26_105
BRAM_L.BRAM_ADDRBWRADDRL4.BRAM_IMUX_ADDRBWRADDRL4 origin:060-bram-cascades !26_104 !26_105 !26_107
BRAM_L.BRAM_ADDRBWRADDRL5.BRAM_CASCINBOT_ADDRBWRADDRU5 origin:060-bram-cascades !26_233 26_232 26_235
BRAM_L.BRAM_ADDRBWRADDRL5.BRAM_CASCINTOP_ADDRBWRADDRU5 origin:060-bram-cascades !26_235 26_232 26_233
BRAM_L.BRAM_ADDRBWRADDRL5.BRAM_IMUX_ADDRBWRADDRL5 origin:060-bram-cascades !26_232 !26_233 !26_235
BRAM_L.BRAM_ADDRBWRADDRL6.BRAM_CASCINBOT_ADDRBWRADDRU6 origin:060-bram-cascades !26_169 26_168 26_171
BRAM_L.BRAM_ADDRBWRADDRL6.BRAM_CASCINTOP_ADDRBWRADDRU6 origin:060-bram-cascades !26_171 26_168 26_169
BRAM_L.BRAM_ADDRBWRADDRL6.BRAM_IMUX_ADDRBWRADDRL6 origin:060-bram-cascades !26_168 !26_169 !26_171
BRAM_L.BRAM_ADDRBWRADDRL7.BRAM_CASCINBOT_ADDRBWRADDRU7 origin:060-bram-cascades !26_185 26_184 26_187
BRAM_L.BRAM_ADDRBWRADDRL7.BRAM_CASCINTOP_ADDRBWRADDRU7 origin:060-bram-cascades !26_187 26_184 26_185
BRAM_L.BRAM_ADDRBWRADDRL7.BRAM_IMUX_ADDRBWRADDRL7 origin:060-bram-cascades !26_184 !26_185 !26_187
BRAM_L.BRAM_ADDRBWRADDRL8.BRAM_CASCINBOT_ADDRBWRADDRU8 origin:060-bram-cascades !26_89 26_88 26_91
BRAM_L.BRAM_ADDRBWRADDRL8.BRAM_CASCINTOP_ADDRBWRADDRU8 origin:060-bram-cascades !26_91 26_88 26_89
BRAM_L.BRAM_ADDRBWRADDRL8.BRAM_IMUX_ADDRBWRADDRL8 origin:060-bram-cascades !26_88 !26_89 !26_91
BRAM_L.BRAM_ADDRBWRADDRL9.BRAM_CASCINBOT_ADDRBWRADDRU9 origin:060-bram-cascades !26_217 26_216 26_219
BRAM_L.BRAM_ADDRBWRADDRL9.BRAM_CASCINTOP_ADDRBWRADDRU9 origin:060-bram-cascades !26_219 26_216 26_217
BRAM_L.BRAM_ADDRBWRADDRL9.BRAM_IMUX_ADDRBWRADDRL9 origin:060-bram-cascades !26_216 !26_217 !26_219
BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_CASCINBOT_ADDRBWRADDRU10 origin:060-bram-cascades !26_153 26_152 26_155
BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_CASCINTOP_ADDRBWRADDRU10 origin:060-bram-cascades !26_155 26_152 26_153
BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_IMUX_ADDRBWRADDRL10 origin:060-bram-cascades !26_152 !26_153 !26_155
BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_CASCINBOT_ADDRBWRADDRU11 origin:060-bram-cascades !26_121 26_120 26_123
BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_CASCINTOP_ADDRBWRADDRU11 origin:060-bram-cascades !26_123 26_120 26_121
BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_IMUX_ADDRBWRADDRL11 origin:060-bram-cascades !26_120 !26_121 !26_123
BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_CASCINBOT_ADDRBWRADDRU12 origin:060-bram-cascades !26_249 26_248 26_251
BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_CASCINTOP_ADDRBWRADDRU12 origin:060-bram-cascades !26_251 26_248 26_249
BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_IMUX_ADDRBWRADDRL12 origin:060-bram-cascades !26_248 !26_249 !26_251
BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_CASCINBOT_ADDRBWRADDRU13 origin:060-bram-cascades !26_137 26_136 26_139
BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_CASCINTOP_ADDRBWRADDRU13 origin:060-bram-cascades !26_139 26_136 26_137
BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_IMUX_ADDRBWRADDRL13 origin:060-bram-cascades !26_136 !26_137 !26_139
BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_CASCINBOT_ADDRBWRADDRU14 origin:060-bram-cascades !26_265 26_264 26_267
BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_CASCINTOP_ADDRBWRADDRU14 origin:060-bram-cascades !26_267 26_264 26_265
BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_IMUX_ADDRBWRADDRL14 origin:060-bram-cascades !26_264 !26_265 !26_267
BRAM_L.BRAM_ADDRBWRADDRU0.BRAM_CASCINBOT_ADDRBWRADDRU0 origin:060-bram-cascades !26_46 26_45 26_47
BRAM_L.BRAM_ADDRBWRADDRU0.BRAM_CASCINTOP_ADDRBWRADDRU0 origin:060-bram-cascades !26_45 26_46 26_47
BRAM_L.BRAM_ADDRBWRADDRU0.BRAM_IMUX_ADDRBWRADDRU0 origin:060-bram-cascades !26_45 !26_46 !26_47
BRAM_L.BRAM_ADDRBWRADDRU1.BRAM_CASCINBOT_ADDRBWRADDRU1 origin:060-bram-cascades !26_62 26_61 26_63
BRAM_L.BRAM_ADDRBWRADDRU1.BRAM_CASCINTOP_ADDRBWRADDRU1 origin:060-bram-cascades !26_61 26_62 26_63
BRAM_L.BRAM_ADDRBWRADDRU1.BRAM_IMUX_ADDRBWRADDRU1 origin:060-bram-cascades !26_61 !26_62 !26_63
BRAM_L.BRAM_ADDRBWRADDRU2.BRAM_CASCINBOT_ADDRBWRADDRU2 origin:060-bram-cascades !26_78 26_77 26_79
BRAM_L.BRAM_ADDRBWRADDRU2.BRAM_CASCINTOP_ADDRBWRADDRU2 origin:060-bram-cascades !26_77 26_78 26_79
BRAM_L.BRAM_ADDRBWRADDRU2.BRAM_IMUX_ADDRBWRADDRU2 origin:060-bram-cascades !26_77 !26_78 !26_79
BRAM_L.BRAM_ADDRBWRADDRU3.BRAM_CASCINBOT_ADDRBWRADDRU3 origin:060-bram-cascades !26_206 26_205 26_207
BRAM_L.BRAM_ADDRBWRADDRU3.BRAM_CASCINTOP_ADDRBWRADDRU3 origin:060-bram-cascades !26_205 26_206 26_207
BRAM_L.BRAM_ADDRBWRADDRU3.BRAM_IMUX_ADDRBWRADDRU3 origin:060-bram-cascades !26_205 !26_206 !26_207
BRAM_L.BRAM_ADDRBWRADDRU4.BRAM_CASCINBOT_ADDRBWRADDRU4 origin:060-bram-cascades !26_110 26_109 26_111
BRAM_L.BRAM_ADDRBWRADDRU4.BRAM_CASCINTOP_ADDRBWRADDRU4 origin:060-bram-cascades !26_109 26_110 26_111
BRAM_L.BRAM_ADDRBWRADDRU4.BRAM_IMUX_ADDRBWRADDRU4 origin:060-bram-cascades !26_109 !26_110 !26_111
BRAM_L.BRAM_ADDRBWRADDRU5.BRAM_CASCINBOT_ADDRBWRADDRU5 origin:060-bram-cascades !26_238 26_237 26_239
BRAM_L.BRAM_ADDRBWRADDRU5.BRAM_CASCINTOP_ADDRBWRADDRU5 origin:060-bram-cascades !26_237 26_238 26_239
BRAM_L.BRAM_ADDRBWRADDRU5.BRAM_IMUX_ADDRBWRADDRU5 origin:060-bram-cascades !26_237 !26_238 !26_239
BRAM_L.BRAM_ADDRBWRADDRU6.BRAM_CASCINBOT_ADDRBWRADDRU6 origin:060-bram-cascades !26_174 26_173 26_175
BRAM_L.BRAM_ADDRBWRADDRU6.BRAM_CASCINTOP_ADDRBWRADDRU6 origin:060-bram-cascades !26_173 26_174 26_175
BRAM_L.BRAM_ADDRBWRADDRU6.BRAM_IMUX_ADDRBWRADDRU6 origin:060-bram-cascades !26_173 !26_174 !26_175
BRAM_L.BRAM_ADDRBWRADDRU7.BRAM_CASCINBOT_ADDRBWRADDRU7 origin:060-bram-cascades !26_190 26_189 26_191
BRAM_L.BRAM_ADDRBWRADDRU7.BRAM_CASCINTOP_ADDRBWRADDRU7 origin:060-bram-cascades !26_189 26_190 26_191
BRAM_L.BRAM_ADDRBWRADDRU7.BRAM_IMUX_ADDRBWRADDRU7 origin:060-bram-cascades !26_189 !26_190 !26_191
BRAM_L.BRAM_ADDRBWRADDRU8.BRAM_CASCINBOT_ADDRBWRADDRU8 origin:060-bram-cascades !26_94 26_93 26_95
BRAM_L.BRAM_ADDRBWRADDRU8.BRAM_CASCINTOP_ADDRBWRADDRU8 origin:060-bram-cascades !26_93 26_94 26_95
BRAM_L.BRAM_ADDRBWRADDRU8.BRAM_IMUX_ADDRBWRADDRU8 origin:060-bram-cascades !26_93 !26_94 !26_95
BRAM_L.BRAM_ADDRBWRADDRU9.BRAM_CASCINBOT_ADDRBWRADDRU9 origin:060-bram-cascades !26_222 26_221 26_223
BRAM_L.BRAM_ADDRBWRADDRU9.BRAM_CASCINTOP_ADDRBWRADDRU9 origin:060-bram-cascades !26_221 26_222 26_223
BRAM_L.BRAM_ADDRBWRADDRU9.BRAM_IMUX_ADDRBWRADDRU9 origin:060-bram-cascades !26_221 !26_222 !26_223
BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_CASCINBOT_ADDRBWRADDRU10 origin:060-bram-cascades !26_158 26_157 26_159
BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_CASCINTOP_ADDRBWRADDRU10 origin:060-bram-cascades !26_157 26_158 26_159
BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_IMUX_ADDRBWRADDRU10 origin:060-bram-cascades !26_157 !26_158 !26_159
BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_CASCINBOT_ADDRBWRADDRU11 origin:060-bram-cascades !26_126 26_125 26_127
BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_CASCINTOP_ADDRBWRADDRU11 origin:060-bram-cascades !26_125 26_126 26_127
BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_IMUX_ADDRBWRADDRU11 origin:060-bram-cascades !26_125 !26_126 !26_127
BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_CASCINBOT_ADDRBWRADDRU12 origin:060-bram-cascades !26_254 26_253 26_255
BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_CASCINTOP_ADDRBWRADDRU12 origin:060-bram-cascades !26_253 26_254 26_255
BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_IMUX_ADDRBWRADDRU12 origin:060-bram-cascades !26_253 !26_254 !26_255
BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_CASCINBOT_ADDRBWRADDRU13 origin:060-bram-cascades !26_142 26_141 26_143
BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_CASCINTOP_ADDRBWRADDRU13 origin:060-bram-cascades !26_141 26_142 26_143
BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_IMUX_ADDRBWRADDRU13 origin:060-bram-cascades !26_141 !26_142 !26_143
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_CASCINBOT_ADDRBWRADDRU14 origin:060-bram-cascades !26_270 26_269 26_271
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_CASCINTOP_ADDRBWRADDRU14 origin:060-bram-cascades !26_269 26_270 26_271
BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_IMUX_ADDRBWRADDRU14 origin:060-bram-cascades !26_269 !26_270 !26_271
BRAM_L.CASCOUT_ARD_ACTIVE origin:060-bram-cascades 26_170
BRAM_L.CASCOUT_BWR_ACTIVE origin:060-bram-cascades 26_172
BRAM_L.EN_SYN origin:028-fifo-config 27_171
BRAM_L.FIRST_WORD_FALL_THROUGH origin:028-fifo-config 27_170
BRAM_L.ZALMOST_EMPTY_OFFSET[0] origin:028-fifo-config 27_288
BRAM_L.ZALMOST_EMPTY_OFFSET[1] origin:028-fifo-config 27_291
BRAM_L.ZALMOST_EMPTY_OFFSET[2] origin:028-fifo-config 27_292
BRAM_L.ZALMOST_EMPTY_OFFSET[3] origin:028-fifo-config 27_293
BRAM_L.ZALMOST_EMPTY_OFFSET[4] origin:028-fifo-config 27_296
BRAM_L.ZALMOST_EMPTY_OFFSET[5] origin:028-fifo-config 27_299
BRAM_L.ZALMOST_EMPTY_OFFSET[6] origin:028-fifo-config 27_300
BRAM_L.ZALMOST_EMPTY_OFFSET[7] origin:028-fifo-config 27_301
BRAM_L.ZALMOST_EMPTY_OFFSET[8] origin:028-fifo-config 27_304
BRAM_L.ZALMOST_EMPTY_OFFSET[9] origin:028-fifo-config 27_307
BRAM_L.ZALMOST_EMPTY_OFFSET[10] origin:028-fifo-config 27_308
BRAM_L.ZALMOST_EMPTY_OFFSET[11] origin:028-fifo-config 27_309
BRAM_L.ZALMOST_EMPTY_OFFSET[12] origin:028-fifo-config 27_312
BRAM_L.ZALMOST_FULL_OFFSET[0] origin:028-fifo-config 27_32
BRAM_L.ZALMOST_FULL_OFFSET[1] origin:028-fifo-config 27_29
BRAM_L.ZALMOST_FULL_OFFSET[2] origin:028-fifo-config 27_28
BRAM_L.ZALMOST_FULL_OFFSET[3] origin:028-fifo-config 27_27
BRAM_L.ZALMOST_FULL_OFFSET[4] origin:028-fifo-config 27_24
BRAM_L.ZALMOST_FULL_OFFSET[5] origin:028-fifo-config 27_21
BRAM_L.ZALMOST_FULL_OFFSET[6] origin:028-fifo-config 27_20
BRAM_L.ZALMOST_FULL_OFFSET[7] origin:028-fifo-config 27_19
BRAM_L.ZALMOST_FULL_OFFSET[8] origin:028-fifo-config 27_16
BRAM_L.ZALMOST_FULL_OFFSET[9] origin:028-fifo-config 27_13
BRAM_L.ZALMOST_FULL_OFFSET[10] origin:028-fifo-config 27_12
BRAM_L.ZALMOST_FULL_OFFSET[11] origin:028-fifo-config 27_11
BRAM_L.ZALMOST_FULL_OFFSET[12] origin:028-fifo-config 27_08
BRAM_L.RAMB18_Y0.DOA_REG origin:025-bram-config 27_69
BRAM_L.RAMB18_Y0.DOB_REG origin:025-bram-config 27_72
BRAM_L.RAMB18_Y0.FIFO_MODE origin:029-bram-fifo-config 27_150
BRAM_L.RAMB18_Y0.IN_USE origin:029-bram-fifo-config 27_100 27_99
BRAM_L.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE origin:025-bram-config !27_96
BRAM_L.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_PERFORMANCE origin:025-bram-config 27_96
BRAM_L.RAMB18_Y0.READ_WIDTH_A_1 origin:025-bram-config !27_35 !27_36 !27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_A_2 origin:025-bram-config !27_36 !27_37 27_35
BRAM_L.RAMB18_Y0.READ_WIDTH_A_4 origin:025-bram-config !27_35 !27_37 27_36
BRAM_L.RAMB18_Y0.READ_WIDTH_A_9 origin:025-bram-config !27_37 27_35 27_36
BRAM_L.RAMB18_Y0.READ_WIDTH_A_18 origin:025-bram-config !27_35 !27_36 27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_B_1 origin:025-bram-config !27_43 !27_44 !27_45
BRAM_L.RAMB18_Y0.READ_WIDTH_B_2 origin:025-bram-config !27_44 !27_45 27_43
BRAM_L.RAMB18_Y0.READ_WIDTH_B_4 origin:025-bram-config !27_43 !27_45 27_44
BRAM_L.RAMB18_Y0.READ_WIDTH_B_9 origin:025-bram-config !27_45 27_43 27_44
BRAM_L.RAMB18_Y0.READ_WIDTH_B_18 origin:025-bram-config !27_43 !27_44 27_45
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_A_REGCE origin:025-bram-config 27_124
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG origin:025-bram-config !27_124
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_B_REGCE origin:025-bram-config 27_125
BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_B_RSTREG origin:025-bram-config !27_125
BRAM_L.RAMB18_Y0.SDP_READ_WIDTH_36 origin:025-bram-config 27_48
BRAM_L.RAMB18_Y0.SDP_WRITE_WIDTH_36 origin:025-bram-config 27_40
BRAM_L.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE origin:025-bram-config 27_64
BRAM_L.RAMB18_Y0.WRITE_MODE_A_READ_FIRST origin:025-bram-config 27_56
BRAM_L.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE origin:025-bram-config 27_68
BRAM_L.RAMB18_Y0.WRITE_MODE_B_READ_FIRST origin:025-bram-config 27_67
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_1 origin:025-bram-config !27_51 !27_52 !27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_2 origin:025-bram-config !27_52 !27_53 27_51
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_4 origin:025-bram-config !27_51 !27_53 27_52
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_9 origin:025-bram-config !27_53 27_51 27_52
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_18 origin:025-bram-config !27_51 !27_52 27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_1 origin:025-bram-config !27_59 !27_60 !27_61
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_2 origin:025-bram-config !27_60 !27_61 27_59
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_4 origin:025-bram-config !27_59 !27_61 27_60
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_9 origin:025-bram-config !27_61 27_59 27_60
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_18 origin:025-bram-config !27_59 !27_60 27_61
BRAM_L.RAMB18_Y0.ZINIT_A[0] origin:025-bram-config 27_73
BRAM_L.RAMB18_Y0.ZINIT_A[1] origin:025-bram-config 27_65
BRAM_L.RAMB18_Y0.ZINIT_A[2] origin:025-bram-config 27_137
BRAM_L.RAMB18_Y0.ZINIT_A[3] origin:025-bram-config 27_121
BRAM_L.RAMB18_Y0.ZINIT_A[4] origin:025-bram-config 27_105
BRAM_L.RAMB18_Y0.ZINIT_A[5] origin:025-bram-config 27_89
BRAM_L.RAMB18_Y0.ZINIT_A[6] origin:025-bram-config 27_57
BRAM_L.RAMB18_Y0.ZINIT_A[7] origin:025-bram-config 27_41
BRAM_L.RAMB18_Y0.ZINIT_A[8] origin:025-bram-config 27_25
BRAM_L.RAMB18_Y0.ZINIT_A[9] origin:025-bram-config 27_09
BRAM_L.RAMB18_Y0.ZINIT_A[10] origin:025-bram-config 27_129
BRAM_L.RAMB18_Y0.ZINIT_A[11] origin:025-bram-config 27_113
BRAM_L.RAMB18_Y0.ZINIT_A[12] origin:025-bram-config 27_97
BRAM_L.RAMB18_Y0.ZINIT_A[13] origin:025-bram-config 27_81
BRAM_L.RAMB18_Y0.ZINIT_A[14] origin:025-bram-config 27_49
BRAM_L.RAMB18_Y0.ZINIT_A[15] origin:025-bram-config 27_33
BRAM_L.RAMB18_Y0.ZINIT_A[16] origin:025-bram-config 27_17
BRAM_L.RAMB18_Y0.ZINIT_A[17] origin:025-bram-config 27_01
BRAM_L.RAMB18_Y0.ZINIT_B[0] origin:025-bram-config 27_79
BRAM_L.RAMB18_Y0.ZINIT_B[1] origin:025-bram-config 27_71
BRAM_L.RAMB18_Y0.ZINIT_B[2] origin:025-bram-config 27_143
BRAM_L.RAMB18_Y0.ZINIT_B[3] origin:025-bram-config 27_127
BRAM_L.RAMB18_Y0.ZINIT_B[4] origin:025-bram-config 27_111
BRAM_L.RAMB18_Y0.ZINIT_B[5] origin:025-bram-config 27_95
BRAM_L.RAMB18_Y0.ZINIT_B[6] origin:025-bram-config 27_63
BRAM_L.RAMB18_Y0.ZINIT_B[7] origin:025-bram-config 27_47
BRAM_L.RAMB18_Y0.ZINIT_B[8] origin:025-bram-config 27_31
BRAM_L.RAMB18_Y0.ZINIT_B[9] origin:025-bram-config 27_15
BRAM_L.RAMB18_Y0.ZINIT_B[10] origin:025-bram-config 27_135
BRAM_L.RAMB18_Y0.ZINIT_B[11] origin:025-bram-config 27_119
BRAM_L.RAMB18_Y0.ZINIT_B[12] origin:025-bram-config 27_103
BRAM_L.RAMB18_Y0.ZINIT_B[13] origin:025-bram-config 27_87
BRAM_L.RAMB18_Y0.ZINIT_B[14] origin:025-bram-config 27_55
BRAM_L.RAMB18_Y0.ZINIT_B[15] origin:025-bram-config 27_39
BRAM_L.RAMB18_Y0.ZINIT_B[16] origin:025-bram-config 27_23
BRAM_L.RAMB18_Y0.ZINIT_B[17] origin:025-bram-config 27_07
BRAM_L.RAMB18_Y0.ZINV_CLKARDCLK origin:025-bram-config 27_107
BRAM_L.RAMB18_Y0.ZINV_CLKBWRCLK origin:025-bram-config 27_109
BRAM_L.RAMB18_Y0.ZINV_ENARDEN origin:025-bram-config 27_112
BRAM_L.RAMB18_Y0.ZINV_ENBWREN origin:025-bram-config 27_115
BRAM_L.RAMB18_Y0.ZINV_REGCLKARDRCLK origin:025-bram-config 27_104
BRAM_L.RAMB18_Y0.ZINV_REGCLKB origin:025-bram-config 27_108
BRAM_L.RAMB18_Y0.ZINV_RSTRAMARSTRAM origin:025-bram-config 27_116
BRAM_L.RAMB18_Y0.ZINV_RSTRAMB origin:025-bram-config 27_117
BRAM_L.RAMB18_Y0.ZINV_RSTREGARSTREG origin:025-bram-config 27_120
BRAM_L.RAMB18_Y0.ZINV_RSTREGB origin:025-bram-config 27_123
BRAM_L.RAMB18_Y0.ZSRVAL_A[0] origin:025-bram-config 27_74
BRAM_L.RAMB18_Y0.ZSRVAL_A[1] origin:025-bram-config 27_66
BRAM_L.RAMB18_Y0.ZSRVAL_A[2] origin:025-bram-config 27_138
BRAM_L.RAMB18_Y0.ZSRVAL_A[3] origin:025-bram-config 27_122
BRAM_L.RAMB18_Y0.ZSRVAL_A[4] origin:025-bram-config 27_106
BRAM_L.RAMB18_Y0.ZSRVAL_A[5] origin:025-bram-config 27_90
BRAM_L.RAMB18_Y0.ZSRVAL_A[6] origin:025-bram-config 27_58
BRAM_L.RAMB18_Y0.ZSRVAL_A[7] origin:025-bram-config 27_42
BRAM_L.RAMB18_Y0.ZSRVAL_A[8] origin:025-bram-config 27_26
BRAM_L.RAMB18_Y0.ZSRVAL_A[9] origin:025-bram-config 27_10
BRAM_L.RAMB18_Y0.ZSRVAL_A[10] origin:025-bram-config 27_130
BRAM_L.RAMB18_Y0.ZSRVAL_A[11] origin:025-bram-config 27_114
BRAM_L.RAMB18_Y0.ZSRVAL_A[12] origin:025-bram-config 27_98
BRAM_L.RAMB18_Y0.ZSRVAL_A[13] origin:025-bram-config 27_82
BRAM_L.RAMB18_Y0.ZSRVAL_A[14] origin:025-bram-config 27_50
BRAM_L.RAMB18_Y0.ZSRVAL_A[15] origin:025-bram-config 27_34
BRAM_L.RAMB18_Y0.ZSRVAL_A[16] origin:025-bram-config 27_18
BRAM_L.RAMB18_Y0.ZSRVAL_A[17] origin:025-bram-config 27_02
BRAM_L.RAMB18_Y0.ZSRVAL_B[0] origin:025-bram-config 27_78
BRAM_L.RAMB18_Y0.ZSRVAL_B[1] origin:025-bram-config 27_70
BRAM_L.RAMB18_Y0.ZSRVAL_B[2] origin:025-bram-config 27_142
BRAM_L.RAMB18_Y0.ZSRVAL_B[3] origin:025-bram-config 27_126
BRAM_L.RAMB18_Y0.ZSRVAL_B[4] origin:025-bram-config 27_110
BRAM_L.RAMB18_Y0.ZSRVAL_B[5] origin:025-bram-config 27_94
BRAM_L.RAMB18_Y0.ZSRVAL_B[6] origin:025-bram-config 27_62
BRAM_L.RAMB18_Y0.ZSRVAL_B[7] origin:025-bram-config 27_46
BRAM_L.RAMB18_Y0.ZSRVAL_B[8] origin:025-bram-config 27_30
BRAM_L.RAMB18_Y0.ZSRVAL_B[9] origin:025-bram-config 27_14
BRAM_L.RAMB18_Y0.ZSRVAL_B[10] origin:025-bram-config 27_134
BRAM_L.RAMB18_Y0.ZSRVAL_B[11] origin:025-bram-config 27_118
BRAM_L.RAMB18_Y0.ZSRVAL_B[12] origin:025-bram-config 27_102
BRAM_L.RAMB18_Y0.ZSRVAL_B[13] origin:025-bram-config 27_86
BRAM_L.RAMB18_Y0.ZSRVAL_B[14] origin:025-bram-config 27_54
BRAM_L.RAMB18_Y0.ZSRVAL_B[15] origin:025-bram-config 27_38
BRAM_L.RAMB18_Y0.ZSRVAL_B[16] origin:025-bram-config 27_22
BRAM_L.RAMB18_Y0.ZSRVAL_B[17] origin:025-bram-config 27_06
BRAM_L.RAMB18_Y1.DOA_REG origin:025-bram-config 27_251
BRAM_L.RAMB18_Y1.DOB_REG origin:025-bram-config 27_248
BRAM_L.RAMB18_Y1.FIFO_MODE origin:029-bram-fifo-config 27_169
BRAM_L.RAMB18_Y1.IN_USE origin:029-bram-fifo-config 27_220 27_221
BRAM_L.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE origin:025-bram-config !27_224
BRAM_L.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_PERFORMANCE origin:025-bram-config 27_224
BRAM_L.RAMB18_Y1.READ_WIDTH_A_1 origin:025-bram-config !27_283 !27_284 !27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_2 origin:025-bram-config !27_283 !27_284 27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_4 origin:025-bram-config !27_283 !27_285 27_284
BRAM_L.RAMB18_Y1.READ_WIDTH_A_9 origin:025-bram-config !27_283 27_284 27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_18 origin:025-bram-config !27_284 !27_285 27_283
BRAM_L.RAMB18_Y1.READ_WIDTH_B_1 origin:025-bram-config !27_275 !27_276 !27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_2 origin:025-bram-config !27_275 !27_276 27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_4 origin:025-bram-config !27_275 !27_277 27_276
BRAM_L.RAMB18_Y1.READ_WIDTH_B_9 origin:025-bram-config !27_275 27_276 27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_18 origin:025-bram-config !27_276 !27_277 27_275
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_A_REGCE origin:025-bram-config 27_196
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG origin:025-bram-config !27_196
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_B_REGCE origin:025-bram-config 27_195
BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_B_RSTREG origin:025-bram-config !27_195
BRAM_L.RAMB18_Y1.SDP_READ_WIDTH_36 origin:025-bram-config 27_272
BRAM_L.RAMB18_Y1.SDP_WRITE_WIDTH_36 origin:025-bram-config 27_280
BRAM_L.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE origin:025-bram-config 27_256
BRAM_L.RAMB18_Y1.WRITE_MODE_A_READ_FIRST origin:025-bram-config 27_264
BRAM_L.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE origin:025-bram-config 27_252
BRAM_L.RAMB18_Y1.WRITE_MODE_B_READ_FIRST origin:025-bram-config 27_253
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_1 origin:025-bram-config !27_267 !27_268 !27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_2 origin:025-bram-config !27_267 !27_268 27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_4 origin:025-bram-config !27_267 !27_269 27_268
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_9 origin:025-bram-config !27_267 27_268 27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_18 origin:025-bram-config !27_268 !27_269 27_267
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_1 origin:025-bram-config !27_259 !27_260 !27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_2 origin:025-bram-config !27_259 !27_260 27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_4 origin:025-bram-config !27_259 !27_261 27_260
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_9 origin:025-bram-config !27_259 27_260 27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_18 origin:025-bram-config !27_260 !27_261 27_259
BRAM_L.RAMB18_Y1.ZINIT_A[0] origin:025-bram-config 27_249
BRAM_L.RAMB18_Y1.ZINIT_A[1] origin:025-bram-config 27_241
BRAM_L.RAMB18_Y1.ZINIT_A[2] origin:025-bram-config 27_313
BRAM_L.RAMB18_Y1.ZINIT_A[3] origin:025-bram-config 27_297
BRAM_L.RAMB18_Y1.ZINIT_A[4] origin:025-bram-config 27_281
BRAM_L.RAMB18_Y1.ZINIT_A[5] origin:025-bram-config 27_265
BRAM_L.RAMB18_Y1.ZINIT_A[6] origin:025-bram-config 27_233
BRAM_L.RAMB18_Y1.ZINIT_A[7] origin:025-bram-config 27_217
BRAM_L.RAMB18_Y1.ZINIT_A[8] origin:025-bram-config 27_201
BRAM_L.RAMB18_Y1.ZINIT_A[9] origin:025-bram-config 27_185
BRAM_L.RAMB18_Y1.ZINIT_A[10] origin:025-bram-config 27_305
BRAM_L.RAMB18_Y1.ZINIT_A[11] origin:025-bram-config 27_289
BRAM_L.RAMB18_Y1.ZINIT_A[12] origin:025-bram-config 27_273
BRAM_L.RAMB18_Y1.ZINIT_A[13] origin:025-bram-config 27_257
BRAM_L.RAMB18_Y1.ZINIT_A[14] origin:025-bram-config 27_225
BRAM_L.RAMB18_Y1.ZINIT_A[15] origin:025-bram-config 27_209
BRAM_L.RAMB18_Y1.ZINIT_A[16] origin:025-bram-config 27_193
BRAM_L.RAMB18_Y1.ZINIT_A[17] origin:025-bram-config 27_177
BRAM_L.RAMB18_Y1.ZINIT_B[0] origin:025-bram-config 27_255
BRAM_L.RAMB18_Y1.ZINIT_B[1] origin:025-bram-config 27_247
BRAM_L.RAMB18_Y1.ZINIT_B[2] origin:025-bram-config 27_319
BRAM_L.RAMB18_Y1.ZINIT_B[3] origin:025-bram-config 27_303
BRAM_L.RAMB18_Y1.ZINIT_B[4] origin:025-bram-config 27_287
BRAM_L.RAMB18_Y1.ZINIT_B[5] origin:025-bram-config 27_271
BRAM_L.RAMB18_Y1.ZINIT_B[6] origin:025-bram-config 27_239
BRAM_L.RAMB18_Y1.ZINIT_B[7] origin:025-bram-config 27_223
BRAM_L.RAMB18_Y1.ZINIT_B[8] origin:025-bram-config 27_207
BRAM_L.RAMB18_Y1.ZINIT_B[9] origin:025-bram-config 27_191
BRAM_L.RAMB18_Y1.ZINIT_B[10] origin:025-bram-config 27_311
BRAM_L.RAMB18_Y1.ZINIT_B[11] origin:025-bram-config 27_295
BRAM_L.RAMB18_Y1.ZINIT_B[12] origin:025-bram-config 27_279
BRAM_L.RAMB18_Y1.ZINIT_B[13] origin:025-bram-config 27_263
BRAM_L.RAMB18_Y1.ZINIT_B[14] origin:025-bram-config 27_231
BRAM_L.RAMB18_Y1.ZINIT_B[15] origin:025-bram-config 27_215
BRAM_L.RAMB18_Y1.ZINIT_B[16] origin:025-bram-config 27_199
BRAM_L.RAMB18_Y1.ZINIT_B[17] origin:025-bram-config 27_183
BRAM_L.RAMB18_Y1.ZINV_CLKARDCLK origin:025-bram-config 27_213
BRAM_L.RAMB18_Y1.ZINV_CLKBWRCLK origin:025-bram-config 27_211
BRAM_L.RAMB18_Y1.ZINV_ENARDEN origin:025-bram-config 27_208
BRAM_L.RAMB18_Y1.ZINV_ENBWREN origin:025-bram-config 27_205
BRAM_L.RAMB18_Y1.ZINV_REGCLKARDRCLK origin:025-bram-config 27_216
BRAM_L.RAMB18_Y1.ZINV_REGCLKB origin:025-bram-config 27_212
BRAM_L.RAMB18_Y1.ZINV_RSTRAMARSTRAM origin:025-bram-config 27_204
BRAM_L.RAMB18_Y1.ZINV_RSTRAMB origin:025-bram-config 27_203
BRAM_L.RAMB18_Y1.ZINV_RSTREGARSTREG origin:025-bram-config 27_200
BRAM_L.RAMB18_Y1.ZINV_RSTREGB origin:025-bram-config 27_197
BRAM_L.RAMB18_Y1.ZSRVAL_A[0] origin:025-bram-config 27_250
BRAM_L.RAMB18_Y1.ZSRVAL_A[1] origin:025-bram-config 27_242
BRAM_L.RAMB18_Y1.ZSRVAL_A[2] origin:025-bram-config 27_314
BRAM_L.RAMB18_Y1.ZSRVAL_A[3] origin:025-bram-config 27_298
BRAM_L.RAMB18_Y1.ZSRVAL_A[4] origin:025-bram-config 27_282
BRAM_L.RAMB18_Y1.ZSRVAL_A[5] origin:025-bram-config 27_266
BRAM_L.RAMB18_Y1.ZSRVAL_A[6] origin:025-bram-config 27_234
BRAM_L.RAMB18_Y1.ZSRVAL_A[7] origin:025-bram-config 27_218
BRAM_L.RAMB18_Y1.ZSRVAL_A[8] origin:025-bram-config 27_202
BRAM_L.RAMB18_Y1.ZSRVAL_A[9] origin:025-bram-config 27_186
BRAM_L.RAMB18_Y1.ZSRVAL_A[10] origin:025-bram-config 27_306
BRAM_L.RAMB18_Y1.ZSRVAL_A[11] origin:025-bram-config 27_290
BRAM_L.RAMB18_Y1.ZSRVAL_A[12] origin:025-bram-config 27_274
BRAM_L.RAMB18_Y1.ZSRVAL_A[13] origin:025-bram-config 27_258
BRAM_L.RAMB18_Y1.ZSRVAL_A[14] origin:025-bram-config 27_226
BRAM_L.RAMB18_Y1.ZSRVAL_A[15] origin:025-bram-config 27_210
BRAM_L.RAMB18_Y1.ZSRVAL_A[16] origin:025-bram-config 27_194
BRAM_L.RAMB18_Y1.ZSRVAL_A[17] origin:025-bram-config 27_178
BRAM_L.RAMB18_Y1.ZSRVAL_B[0] origin:025-bram-config 27_254
BRAM_L.RAMB18_Y1.ZSRVAL_B[1] origin:025-bram-config 27_246
BRAM_L.RAMB18_Y1.ZSRVAL_B[2] origin:025-bram-config 27_318
BRAM_L.RAMB18_Y1.ZSRVAL_B[3] origin:025-bram-config 27_302
BRAM_L.RAMB18_Y1.ZSRVAL_B[4] origin:025-bram-config 27_286
BRAM_L.RAMB18_Y1.ZSRVAL_B[5] origin:025-bram-config 27_270
BRAM_L.RAMB18_Y1.ZSRVAL_B[6] origin:025-bram-config 27_238
BRAM_L.RAMB18_Y1.ZSRVAL_B[7] origin:025-bram-config 27_222
BRAM_L.RAMB18_Y1.ZSRVAL_B[8] origin:025-bram-config 27_206
BRAM_L.RAMB18_Y1.ZSRVAL_B[9] origin:025-bram-config 27_190
BRAM_L.RAMB18_Y1.ZSRVAL_B[10] origin:025-bram-config 27_310
BRAM_L.RAMB18_Y1.ZSRVAL_B[11] origin:025-bram-config 27_294
BRAM_L.RAMB18_Y1.ZSRVAL_B[12] origin:025-bram-config 27_278
BRAM_L.RAMB18_Y1.ZSRVAL_B[13] origin:025-bram-config 27_262
BRAM_L.RAMB18_Y1.ZSRVAL_B[14] origin:025-bram-config 27_230
BRAM_L.RAMB18_Y1.ZSRVAL_B[15] origin:025-bram-config 27_214
BRAM_L.RAMB18_Y1.ZSRVAL_B[16] origin:025-bram-config 27_198
BRAM_L.RAMB18_Y1.ZSRVAL_B[17] origin:025-bram-config 27_182
BRAM_L.RAMB36.EN_ECC_READ origin:027-bram36-config 27_175
BRAM_L.RAMB36.EN_ECC_WRITE origin:027-bram36-config 27_162
BRAM_L.RAMB36.RAM_EXTENSION_A_LOWER origin:027-bram36-config 27_188
BRAM_L.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER origin:027-bram36-config !27_188
BRAM_L.RAMB36.RAM_EXTENSION_B_LOWER origin:027-bram36-config 27_187
BRAM_L.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER origin:027-bram36-config !27_187
BRAM_L.RAMB36.BRAM36_READ_WIDTH_A_1 origin:027-bram36-config 27_184
BRAM_L.RAMB36.BRAM36_READ_WIDTH_B_1 origin:027-bram36-config 27_181
BRAM_L.RAMB36.BRAM36_WRITE_WIDTH_A_1 origin:027-bram36-config 27_180
BRAM_L.RAMB36.BRAM36_WRITE_WIDTH_B_1 origin:027-bram36-config 27_179