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tile_type_RIOI3.json
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tile_type_RIOI3.json
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{
"pips": {
"RIOI3.IOI_BYP3_0->IOI_IMUX_RC0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_IMUX_RC0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP3_0"
},
"RIOI3.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_RCLK_DIV_CLR0_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP3_0"
},
"RIOI3.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_RCLK_DIV_CLR3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP3_0"
},
"RIOI3.IOI_BYP3_1->IOI_IMUX_RC3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_IMUX_RC3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP3_1"
},
"RIOI3.IOI_BYP3_1->IOI_RCLK_DIV_CE0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_RCLK_DIV_CE0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP3_1"
},
"RIOI3.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_RCLK_DIV_CE3_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP3_1"
},
"RIOI3.IOI_BYP4_0->IOI_IMUX_RC1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_IMUX_RC1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP4_0"
},
"RIOI3.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_RCLK_DIV_CLR1_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP4_0"
},
"RIOI3.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_RCLK_DIV_CLR2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP4_0"
},
"RIOI3.IOI_BYP4_1->IOI_IMUX_RC2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_IMUX_RC2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP4_1"
},
"RIOI3.IOI_BYP4_1->IOI_RCLK_DIV_CE1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_RCLK_DIV_CE1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP4_1"
},
"RIOI3.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_RCLK_DIV_CE2_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP4_1"
},
"RIOI3.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_IDELAY1_CINVCTRL",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP6_0"
},
"RIOI3.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_IDELAY0_CINVCTRL",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP6_1"
},
"RIOI3.IOI_BYP7_0->RIOI3_IDELAY1_IFDLY2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "RIOI3_IDELAY1_IFDLY2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP7_0"
},
"RIOI3.IOI_BYP7_1->RIOI3_IDELAY0_IFDLY2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "RIOI3_IDELAY0_IFDLY2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP7_1"
},
"RIOI3.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_ILOGIC1_CLKDIV",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_CLK0_0"
},
"RIOI3.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_ILOGIC1_CLKDIVP",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_CLK0_0"
},
"RIOI3.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_ILOGIC0_CLKDIV",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_CLK0_1"
},
"RIOI3.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_ILOGIC0_CLKDIVP",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_CLK0_1"
},
"RIOI3.IOI_CLK1_0->IOI_IDELAY1_C": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_IDELAY1_C",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_CLK1_0"
},
"RIOI3.IOI_CLK1_1->IOI_IDELAY0_C": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_IDELAY0_C",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_CLK1_1"
},
"RIOI3.IOI_CTRL0_0->IOI_OLOGIC1_SR": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_OLOGIC1_SR",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_CTRL0_0"
},
"RIOI3.IOI_CTRL0_1->IOI_OLOGIC0_SR": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_OLOGIC0_SR",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_CTRL0_1"
},
"RIOI3.IOI_CTRL1_0->IOI_ILOGIC1_SR": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_ILOGIC1_SR",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_CTRL1_0"
},
"RIOI3.IOI_CTRL1_1->IOI_ILOGIC0_SR": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_ILOGIC0_SR",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_CTRL1_1"
},
"RIOI3.IOI_FAN4_0->RIOI3_IDELAY1_IFDLY0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "RIOI3_IDELAY1_IFDLY0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_FAN4_0"
},
"RIOI3.IOI_FAN4_1->RIOI3_IDELAY0_IFDLY0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "RIOI3_IDELAY0_IFDLY0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_FAN4_1"
},
"RIOI3.IOI_FAN5_0->RIOI3_IDELAY1_IFDLY1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "RIOI3_IDELAY1_IFDLY1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_FAN5_0"
},
"RIOI3.IOI_FAN5_1->RIOI3_IDELAY0_IFDLY1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "RIOI3_IDELAY0_IFDLY1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_FAN5_1"
},
"RIOI3.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_LOGIC_OUTS20_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_IDELAY0_CNTVALUEOUT0"
},
"RIOI3.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_LOGIC_OUTS1_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_IDELAY0_CNTVALUEOUT1"
},
"RIOI3.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_LOGIC_OUTS19_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_IDELAY0_CNTVALUEOUT2"
},
"RIOI3.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_LOGIC_OUTS15_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_IDELAY0_CNTVALUEOUT3"
},
"RIOI3.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_LOGIC_OUTS11_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_IDELAY0_CNTVALUEOUT4"
},
"RIOI3.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_LOGIC_OUTS20_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_IDELAY1_CNTVALUEOUT0"
},
"RIOI3.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_LOGIC_OUTS1_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_IDELAY1_CNTVALUEOUT1"
},
"RIOI3.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_LOGIC_OUTS19_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_IDELAY1_CNTVALUEOUT2"
},
"RIOI3.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_LOGIC_OUTS15_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_IDELAY1_CNTVALUEOUT3"
},
"RIOI3.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_LOGIC_OUTS11_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_IDELAY1_CNTVALUEOUT4"
},
"RIOI3.IOI_IDELAYCTRL_DNPULSEOUT->IOI_LOGIC_OUTS13_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_LOGIC_OUTS13_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_IDELAYCTRL_DNPULSEOUT"
},
"RIOI3.IOI_IDELAYCTRL_OUTN1->IOI_LOGIC_OUTS13_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_LOGIC_OUTS13_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_IDELAYCTRL_OUTN1"
},
"RIOI3.IOI_IDELAYCTRL_OUTN65->IOI_LOGIC_OUTS16_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_LOGIC_OUTS16_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_IDELAYCTRL_OUTN65"
},
"RIOI3.IOI_IDELAYCTRL_RDY->IOI_LOGIC_OUTS22_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_LOGIC_OUTS22_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_IDELAYCTRL_RDY"
},
"RIOI3.IOI_IDELAYCTRL_UPPULSEOUT->IOI_LOGIC_OUTS16_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_LOGIC_OUTS16_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_IDELAYCTRL_UPPULSEOUT"
},
"RIOI3.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": {
"can_invert": "0",
"dst_to_src": {
"delay": [
"0.004",
"0.015",
"0.027",
"0.030"
],
"in_cap": "0.000",
"res": "0.0"
},
"dst_wire": "IOI_LOGIC_OUTS18_1",
"is_directional": "1",
"is_pass_transistor": 0,
"is_pseudo": "0",
"src_to_dst": {
"delay": [
"0.004",
"0.015",
"0.027",
"0.030"
],
"in_cap": "0.000",
"res": "0.0"
},
"src_wire": "IOI_ILOGIC0_O"
},
"RIOI3.IOI_ILOGIC0_O->RIOI_I2GCLK_TOP0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "RIOI_I2GCLK_TOP0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_ILOGIC0_O"
},
"RIOI3.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_LOGIC_OUTS0_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_ILOGIC0_Q1"
},
"RIOI3.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_LOGIC_OUTS23_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_ILOGIC0_Q2"
},
"RIOI3.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_LOGIC_OUTS9_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_ILOGIC0_Q3"
},
"RIOI3.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_LOGIC_OUTS10_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_ILOGIC0_Q4"
},
"RIOI3.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_LOGIC_OUTS14_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_ILOGIC0_Q5"
},
"RIOI3.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_LOGIC_OUTS3_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_ILOGIC0_Q6"
},
"RIOI3.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_LOGIC_OUTS7_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_ILOGIC0_Q7"
},
"RIOI3.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_LOGIC_OUTS8_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},