The encoding table for the bit manipulation extension is not rendered

[melonedo]

Issue Description

The encoding table for the bit manipulation extension is not rendered. There is source code for this table but it is not rendered in GitHub preview.

cv32e40p/docs/source/instruction_set_extensions.rst

Lines 648 to 705 in 0391e5c

	Bit Manipulation Encoding
	^^^^^^^^^^^^^^^^^^^^^^^^^
	.. table:: Immediate Bit Manipulation operations encoding
	:name: Immediate Bit Manipulation operations encoding
	:width: 50
	:widths: 5 14 13 5 8 6 16 33
	:class: no-scrollbar-table
	+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
	| 31: 30 | 29 : 25 | 24 : 20 | 19 : 15 | 14 : 12 | 11 : 7 | 6 : 0 | |
	+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
	| **f2** | **ls3[4:0]** | **ls2[4:0]** | **rs1** | **funct3** | **rD** | **opcode** | **Mnemonic** |
	+========+======================+===============+=========+============+========+============+====================================+
	| 00 | Luimm5[4:0] | Iuimm5[4:0] | src | 000 | dest | 101 1011 | **cv.extract rD, rs1, Is3, Is2** |
	+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
	| 01 | Luimm5[4:0] | Iuimm5[4:0] | src | 000 | dest | 101 1011 | **cv.extractu rD, rs1, Is3, Is2** |
	+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
	| 10 | Luimm5[4:0] | Iuimm5[4:0] | src | 000 | dest | 101 1011 | **cv.insert rD, rs1, Is3, Is2** |
	+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
	| 00 | Luimm5[4:0] | Iuimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bclr rD, rs1, Is3, Is2** |
	+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
	| 01 | Luimm5[4:0] | Iuimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bset rD, rs1, Is3, Is2** |
	+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
	| 11 | 000, Luimm2[1:0] | Iuimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bitrev rD, rs1, Is3, Is2** |
	+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
	.. table:: Register Bit Manipulation operations encoding
	:name: Register Bit Manipulation operations encoding
	:width: 50
	:widths: 19 13 5 8 6 16 33
	:class: no-scrollbar-table
	+------------+---------+---------+------------+--------+------------+--------------------------------+
	| 31 : 25 | 24 : 20 | 19 : 15 | 14 : 12 | 11 : 7 | 6 : 0 | |
	+------------+---------+---------+------------+--------+------------+--------------------------------+
	| **funct7** | **rs2** | **rs1** | **funct3** | **rD** | **opcode** | |
	+============+=========+=========+============+========+============+================================+
	| 001 1000 | src2 | src1 | 011 | dest | 010 1011 | **cv.extractr rD, rs1, rs2** |
	+------------+---------+---------+------------+--------+------------+--------------------------------+
	| 001 1001 | src2 | src1 | 011 | dest | 010 1011 | **cv.extractur rD, rs1, rs2** |
	+------------+---------+---------+------------+--------+------------+--------------------------------+
	| 001 1010 | src2 | src1 | 011 | dest | 010 1011 | **cv.insertr rD, rs1, rs2** |
	+------------+---------+---------+------------+--------+------------+--------------------------------+
	| 001 1100 | src2 | src1 | 011 | dest | 010 1011 | **cv.bclrr rD, rs1, rs2** |
	+------------+---------+---------+------------+--------+------------+--------------------------------+
	| 001 1101 | src2 | scr1 | 011 | dest | 010 1011 | **cv.bsetr rD, rs1, rs2** |
	+------------+---------+---------+------------+--------+------------+--------------------------------+
	| 010 0000 | src2 | src1 | 011 | dest | 010 1011 | **cv.ror rD, rs1, rs2** |
	+------------+---------+---------+------------+--------+------------+--------------------------------+
	| 010 0001 | 00000 | src1 | 011 | dest | 010 1011 | **cv.ff1 rD, rs1** |
	+------------+---------+---------+------------+--------+------------+--------------------------------+
	| 010 0010 | 00000 | src1 | 011 | dest | 010 1011 | **cv.fl1 rD, rs1** |
	+------------+---------+---------+------------+--------+------------+--------------------------------+
	| 010 0011 | 00000 | src1 | 011 | dest | 010 1011 | **cv.clb rD, rs1** |
	+------------+---------+---------+------------+--------+------------+--------------------------------+
	| 010 0100 | 00000 | src1 | 011 | dest | 010 1011 | **cv.cnt rD, rs1** |
	+------------+---------+---------+------------+--------+------------+--------------------------------+

Component

Component:Doc

[MikeOpenHWGroup]

Hi @melonedo, thanks for your interest in CV32E40P. GitHub supports a subset of Markdown and therefore the GitHub preview renderings are not complete. The best way to view the User Manual is on ReadTheDocs, the bit-manip encoding chapter is here. Note that you can always find the link to the latest version of the CV32E40P User Manual under the "About" section on the upper-right of the repo's home page.

Let us know if that resolves this issue for you. Thanks.

[pascalgouedo]

Hi @melonedo
Thanks for figuring out this. There was 1 remaining "width" command on those 2 encoding tables.
I removed them locally and saw that it restored github rendering while leaving generated sphynx html and pdf the same as before.
Will commit my update.

[pascalgouedo]

Corrected with PR #818