diff --git a/src/uct/ib/rc/accel/rc_mlx5_common.c b/src/uct/ib/rc/accel/rc_mlx5_common.c
index 9bdbc6005a2b..afca3ba27a6c 100644
--- a/src/uct/ib/rc/accel/rc_mlx5_common.c
+++ b/src/uct/ib/rc/accel/rc_mlx5_common.c
@@ -91,6 +91,7 @@ unsigned uct_rc_mlx5_iface_srq_post_recv(uct_rc_mlx5_iface_common_t *iface)
                       sizeof(struct mlx5_wqe_srq_next_seg));
 
     ucs_assert(UCS_CIRCULAR_COMPARE16(srq->ready_idx, <=, srq->free_idx));
+    ucs_assert(rc_iface->rx.srq.available > 0);
 
     wqe_index = srq->ready_idx;
     for (;;) {
@@ -140,9 +141,13 @@ unsigned uct_rc_mlx5_iface_srq_post_recv(uct_rc_mlx5_iface_common_t *iface)
 
 void uct_rc_mlx5_iface_common_prepost_recvs(uct_rc_mlx5_iface_common_t *iface)
 {
-    iface->super.rx.srq.available = iface->super.rx.srq.quota;
-    iface->super.rx.srq.quota     = 0;
-    uct_rc_mlx5_iface_srq_post_recv(iface);
+    /* prepost recvs only if quota available
+     * (recvs were not preposted before) */ 
+    if (iface->super.rx.srq.quota > 0) { 
+        iface->super.rx.srq.available = iface->super.rx.srq.quota;
+        iface->super.rx.srq.quota     = 0;
+        uct_rc_mlx5_iface_srq_post_recv(iface);
+    }
 }
 
 #define UCT_RC_MLX5_DEFINE_ATOMIC_LE_HANDLER(_bits) \