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    292 repositories

    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
      asiccpuvectorriscvararvvrv64gcv
      C
      •
      Other
      •127•357•60•11•Updated Oct 11, 2024Oct 11, 2024

    • chimera

      Public
      Python
      •
      Other
      •1•8•9•2•Updated Oct 11, 2024Oct 11, 2024

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicriscvsystemverilogrtl-designfpgasimulation
      Verilog
      •
      Other
      •41•188•7•21•Updated Oct 10, 2024Oct 10, 2024

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •679•15•1•7•Updated Oct 10, 2024Oct 10, 2024

    • pulp-trainlib

      Public
      Floating-Point Optimized On-Device Learning Library for the PULP Platform.
      C
      •
      Apache License 2.0
      •15•25•4•3•Updated Oct 10, 2024Oct 10, 2024

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •2•13•1•0•Updated Oct 10, 2024Oct 10, 2024

    • ITA

      Public
      SystemVerilog
      •
      Other
      •2•9•0•2•Updated Oct 10, 2024Oct 10, 2024

    • riscv-opcodes

      Public
      RISC-V Opcodes
      Python
      •
      Other
      •299•7•0•4•Updated Oct 9, 2024Oct 9, 2024

    • obi

      Public
      OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
      SystemVerilog
      •
      Other
      •1•9•0•3•Updated Oct 9, 2024Oct 9, 2024

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •142•502•28•4•Updated Oct 9, 2024Oct 9, 2024

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •257•1.1k•42•13•Updated Oct 8, 2024Oct 8, 2024

    • axi_rt

      Public
      SystemVerilog
      •
      Other
      •3•2•3•0•Updated Oct 8, 2024Oct 8, 2024

    • mempool

      Public
      A 256-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •44•268•3•7•Updated Oct 8, 2024Oct 8, 2024

    • astral

      Public
      A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.
      cfpgaspaceacceleratorriscvsystemverilogmulticoresafety-criticalheterogeneous-computing
      Tcl
      •
      Other
      •13•5•0•6•Updated Oct 8, 2024Oct 8, 2024

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •21•127•10•3•Updated Oct 8, 2024Oct 8, 2024

    • quadrilatero

      Public
      matrix-coprocessor for RISC-V
      C
      •
      Other
      •1•6•0•0•Updated Oct 4, 2024Oct 4, 2024

    • pulp-ethernet

      Public
      SystemVerilog
      •
      Other
      •1•8•0•2•Updated Oct 4, 2024Oct 4, 2024

    • occamy

      Public
      A high-efficiency system-on-chip for floating-point compute workloads.
      Python
      •
      Apache License 2.0
      •11•15•7•1•Updated Oct 3, 2024Oct 3, 2024

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •49•49•13•6•Updated Oct 3, 2024Oct 3, 2024

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •15•68•1•1•Updated Oct 3, 2024Oct 3, 2024

    • memory_island

      Public
      An interleaved high-throughput low-contention L2 scratchpad memory.
      SystemVerilog
      •
      Other
      •0•1•4•3•Updated Oct 3, 2024Oct 3, 2024

    • cheshire-ihp130-o

      Public
      Tcl
      •
      Other
      •4•23•1•0•Updated Oct 2, 2024Oct 2, 2024

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •21•56•4•3•Updated Oct 1, 2024Oct 1, 2024

    • cluster_icache

      Public
      An instruction cache for processor clusters, originally developed for the snitch cluster.
      SystemVerilog
      •
      Other
      •1•2•0•5•Updated Oct 1, 2024Oct 1, 2024

    • dyn_spm

      Public
      SystemVerilog
      •
      Other
      •0•2•1•0•Updated Sep 28, 2024Sep 28, 2024

    • hwpe-stream

      Public
      IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
      SystemVerilog
      •
      Other
      •18•18•1•5•Updated Sep 27, 2024Sep 27, 2024

    • hyperbus

      Public
      SystemVerilog
      •
      Other
      •2•18•1•2•Updated Sep 27, 2024Sep 27, 2024

    • cvfpu

      Public
      Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
      SystemVerilog
      •
      Apache License 2.0
      •113•12•0•4•Updated Sep 27, 2024Sep 27, 2024

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •26•89•8•8•Updated Sep 26, 2024Sep 26, 2024

    • register_interface

      Public
      Generic Register Interface (contains various adapters)
      SystemVerilog
      •
      Other
      •24•96•1•0•Updated Sep 25, 2024Sep 25, 2024