NTUEE IC Design 23Fall HW4
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Updated
Dec 12, 2023 - Verilog
NTUEE IC Design 23Fall HW4
NTUEE IC Design 23Fall HW3
A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-frequency) algorithm. The average SNR = 58.76.
A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
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