A 32-bit MIPS instruction set CPU's design and realization based on Logisim Platform
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Updated
Feb 26, 2023
A 32-bit MIPS instruction set CPU's design and realization based on Logisim Platform
MIPS CPU for system design course project.
Trabajo práctico especial. Materia: Arquitectura de computadoras I. Año: 2017. UNICEN.
A five stage pipeline processor for MIPS32 Release 1. Frequency > 120MHz.
A complete hardware description of a pipeline MIPS processor in SystemVerilog that can execute integer assembly code implemented on the Altera DE2-115 FPGA. It also has the ALMa Mips Mounter built-in.
BUAA Computer Organization Project7 CPU pipeplus
Multiple cycle cpu(using verilog) based on MIPS.
BUAA Computer Organization Project4 CPU monocycle
Simple single cycle processor for modified reduced MIPS32 instruction set.
This is a university project. It is an implementation ant testing of MIPS processor in verilog. It is not synthesizable yet
Computer Architecture I (University of Aveiro)
An ELF parser, which calculates stack usage for embedded mips microcontroller, especially for Microchip's XC32 compiler
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