It is a 32-bit RISC-V cpu model designed in Verilog.
it implements all 37 instructions of the RV32I Instruction set except the instructions for CSR.
the CPU model is CPU, this file only models the cpu, instruction code memory and ram needs to be connected to its ports separately
======= the instruction set encoding supported by this is given here. all these instructions are taken from the official RV32I
the CPU model is CPU, this file only models the CPU, instruction code memory and RAM needs to be connected to its ports separately
![[vivado-schematic]](/Aniketkumarroy/NovaEdge32/blob/main/vivado-schematic.png)
![[vivado-schematic]](/Aniketkumarroy/NovaEdge32/blob/main/schematic.png)