The purpose of this project was to design an accelarator using C and design tools from Xilinx, like the Vivado High level Synthesis for the inner design of the Accelarator and the SDSoC to design the transfer of the data in Zynq-7000.
The function that was accelarated was given as reference code.
The project is seperated in 4 phases.
1)Creation of myFunc_Accel and myLib.h. Simplification of the given function myFunc so that can be easily translated in FPGA logic. 2)Use of Vivado HLS and its directives to create the Architecture of the Accelarator. 3)Use of the SDSoC and various data transfer protocols to achieve maximum efficiency. 4)Report of the project (written in Greek).