After completing the course, I have gained excellent understanding of pipelining and its implementation in assembly language and different types of parallelism and their strengths and weaknesses.
- modified the
4-stage pipelined processor
to includeload word (lw)
andstore word(sw)
instructions - transformed it into a
5 stage pipelined processor
- analyzed the operation of 5 stage pipelined data path and
simulated
the LW and sw instructions along with rtype and addi instructions
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Overview of basic computer architecture
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Instruction Set Architecture Design
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Micro-architecture Design
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Memory Systems and I/O Design
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Instruction-Level Parallelism
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Data-Level Parallelism
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Thread-Level Parallelism
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Emerging Computing Trends