Verilog-RTLDesign-AESEngine

AES encryption co-processor in Verilog. For more details see readme.pdf

Name		Name	Last commit message	Last commit date
Latest commit History 49 Commits
build		build
gtkwave		gtkwave
output-console		output-console
output-waveform-sc		output-waveform-sc
simulation		simulation
syn_ref		syn_ref
.AES_PAD.v.swp		.AES_PAD.v.swp
.gitattributes		.gitattributes
.gitignore		.gitignore
AES_PAD.v		AES_PAD.v
LICENSE		LICENSE
README.md		README.md
aes_engine.v		aes_engine.v
aes_engine_tb.v		aes_engine_tb.v
engine_key_generator.v		engine_key_generator.v
engine_key_generator_tb.v		engine_key_generator_tb.v
engine_round_transformer.v		engine_round_transformer.v
engine_round_transformer_tb.v		engine_round_transformer_tb.v
input_interface.v		input_interface.v
input_interface_tb.v		input_interface_tb.v
output_interface.v		output_interface.v
output_interface_tb.v		output_interface_tb.v
readme.pdf		readme.pdf
simulate.sh		simulate.sh

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