This repository contains FPGA design projects on the Terasic DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite. It includes VHDL/Verilog codes for digital circuits, verification and testbenches viewed on GTKWave, QSF pin assignments, RTL simulations, and designs with IP cores, FSMs, communication protocols, DSP, and microcontrollers.
-
Notifications
You must be signed in to change notification settings - Fork 0
This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. The projects primarily focus on Finite State Machines (FSMs) and communication protocols, implemented in VHDL. Each project includes HDL code, testbenches, simulations, and qsf files for pin assignments.
Samuel-101/FPGA
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Folders and files
| Name | Name | Last commit message | Last commit date | |
|---|---|---|---|---|
Repository files navigation
About
This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. The projects primarily focus on Finite State Machines (FSMs) and communication protocols, implemented in VHDL. Each project includes HDL code, testbenches, simulations, and qsf files for pin assignments.
Topics
Resources
Stars
Watchers
Forks
Releases
No releases published
Packages 0
No packages published