[BUG] software read-only, hardware write-only not working with write enable

[miguel9554]

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Describe the bug

When generating a register map which contains a SW RO HW WO with HW write-enable, tool fails.

Expected behavior

A SW RO HW WO write-enable should result in a storage element, written everytime write enable is asserted. This case is not mentioned in table 12 of the systemRDL spec, so in principle is not prohibited by the spec.

Additional context

Following regmap results in the error:

regfile fir_filter_regfile {
    default regwidth = 32;
    reg {
        field { sw = r; hw = w; we=true; fieldwidth = 32; } swr_hww_we_field;
    } test_reg;
};

Generating SystemVerilog RAL model (regblock)...
peakrdl regblock -o output/rtl --cpuif axi4-lite fir_filter_regmap.rdl
fir_filter_regfile.rdl:4:33: error: Use of 'we' property on field 'swr_hww_we_field' that does not implement storage does not make sense
        field { sw = r; hw = w; we=true; fieldwidth = 32; } swr_hww_we_field;
                                ^^
fatal: Elaborate aborted due to previous errors
make: *** [Makefile:36: output/rtl/fir_filter_regmap.sv] Error 1