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30 Open 72 Closed
30 Open 72 Closed
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Issues list

[BUG] intr field can miss events during SW writes
#120 opened Oct 4, 2024 by hughjackson
1 task done
1
[FEATURE] AHB interface support feature request New feature or request
#119 opened Oct 1, 2024 by Blebowski
3
[BUG] software read-only, hardware write-only not working with write enable
#118 opened Aug 26, 2024 by miguel9554
1 task done
[BUG] Incorred bit extraction on external component address assignment
#116 opened Jul 16, 2024 by apstrike
[BUG] reg after external mem is only generated if not in regfile or addrmap
#115 opened Jul 10, 2024 by paul-demo
1 task done
Saturating counters perform inequality check twice in generated logic
#114 opened Jun 7, 2024 by paul-demo
[BUG] Genus unsynthesizable error on rising/falling edge interrupt field
#113 opened May 25, 2024 by BertVerrycken
1 task done
[FEATURE] Parameters in regblock package
#112 opened May 24, 2024 by benoitdenkinger
External registers packed struct
#111 opened May 23, 2024 by benoitdenkinger
1
[BUG] memory size is not calulated correctly invalid This doesn't seem right
#110 opened May 23, 2024 by arnonsha
4
Put pragmas around assertions
#104 opened Apr 28, 2024 by Blebowski
2
More optimized readback stage RTL generation invalid This doesn't seem right wontfix This will not be worked on
#103 opened Apr 27, 2024 by Blebowski
4
Clock gating support wontfix This will not be worked on
#102 opened Apr 27, 2024 by Blebowski
4
Unaligned external addressable components
#101 opened Apr 23, 2024 by maltaisn
Interface data width vs register width vs access width
#100 opened Apr 18, 2024 by jscheid-ventana
1
hwset on multibit field feature request New feature or request
#99 opened Apr 16, 2024 by darrylring
5
unconditional is None # Can only have one unconditional assignment per field bug Something isn't working
#93 opened Apr 3, 2024 by xachb
2
Casting For-Loop Iterator to Match Address Width in Decoding Logic
#92 opened Apr 2, 2024 by leolitenstorrent
infer accesswidth when only external components in RDL
#90 opened Mar 21, 2024 by saberxt
4
User defined property for specifying cpuif
#77 opened Dec 14, 2023 by RasmusGOlsen
1
1
Raising an error for unauthorized read or write feature request New feature or request
#76 opened Dec 11, 2023 by imerkado91
6
During export, check for identifier collisions in output feature request New feature or request
#73 opened Nov 7, 2023 by amykyta3
VHDL Package Compatibilty feature request New feature or request
#61 opened Aug 16, 2023 by eddlestar
2
Feature Request: Option to remove buffer stage from AXI read/write feature request New feature or request
#47 opened Jun 12, 2023 by leolitenstorrent
@amykyta3
6
Verilator support
#41 opened Jun 1, 2023 by Risto97
4
ProTip! Exclude everything labeled bug with -label:bug.