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vivado.jou
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#-----------------------------------------------------------
# Vivado v2016.4 (64-bit)
# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
# Start of session at: Thu Sep 28 12:55:30 2017
# Process ID: 932
# Current directory: D:/Development/FPGA/InterNoC
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent11148 D:\Development\FPGA\InterNoC\InterNoC.xpr
# Log file: D:/Development/FPGA/InterNoC/vivado.log
# Journal file: D:/Development/FPGA/InterNoC\vivado.jou
#-----------------------------------------------------------
start_gui
open_project D:/Development/FPGA/InterNoC/InterNoC.xpr
generate_target Simulation [get_files D:/Development/FPGA/InterNoC/InterNoC.srcs/sources_1/bd/DemoInterconnect/DemoInterconnect.bd]
export_ip_user_files -of_objects [get_files D:/Development/FPGA/InterNoC/InterNoC.srcs/sources_1/bd/DemoInterconnect/DemoInterconnect.bd] -no_script -force -quiet
launch_simulation
generate_target Simulation [get_files D:/Development/FPGA/InterNoC/InterNoC.srcs/sources_1/bd/DemoInterconnect/DemoInterconnect.bd]
export_ip_user_files -of_objects [get_files D:/Development/FPGA/InterNoC/InterNoC.srcs/sources_1/bd/DemoInterconnect/DemoInterconnect.bd] -no_script -force -quiet
launch_simulation
set_property -name {xsim.compile.incremental} -value {true} -objects [get_filesets sim_1]
generate_target Simulation [get_files D:/Development/FPGA/InterNoC/InterNoC.srcs/sources_1/bd/DemoInterconnect/DemoInterconnect.bd]
export_ip_user_files -of_objects [get_files D:/Development/FPGA/InterNoC/InterNoC.srcs/sources_1/bd/DemoInterconnect/DemoInterconnect.bd] -no_script -force -quiet
launch_simulation
generate_target Simulation [get_files D:/Development/FPGA/InterNoC/InterNoC.srcs/sources_1/bd/DemoInterconnect/DemoInterconnect.bd]
export_ip_user_files -of_objects [get_files D:/Development/FPGA/InterNoC/InterNoC.srcs/sources_1/bd/DemoInterconnect/DemoInterconnect.bd] -no_script -force -quiet
launch_simulation
generate_target Simulation [get_files D:/Development/FPGA/InterNoC/InterNoC.srcs/sources_1/bd/DemoInterconnect/DemoInterconnect.bd]
export_ip_user_files -of_objects [get_files D:/Development/FPGA/InterNoC/InterNoC.srcs/sources_1/bd/DemoInterconnect/DemoInterconnect.bd] -no_script -force -quiet
launch_simulation
source DemoInterconnect_TestBench.tcl
restart
relaunch_sim
run 500 us
restart
relaunch_sim
run 100 ns
save_wave_config {D:/Development/FPGA/InterNoC/DemoInterconnect_TestBench_behav.wcfg}
add_files -fileset sim_1 -norecurse D:/Development/FPGA/InterNoC/DemoInterconnect_TestBench_behav.wcfg
set_property xsim.view D:/Development/FPGA/InterNoC/DemoInterconnect_TestBench_behav.wcfg [get_filesets sim_1]
relaunch_sim
open_bd_design {D:/Development/FPGA/InterNoC/InterNoC.srcs/sources_1/bd/DemoInterconnect/DemoInterconnect.bd}
update_ip_catalog -rebuild -scan_changes
report_ip_status -name ip_status
upgrade_ip [get_ips {DemoInterconnect_interface_axi_master_0_0 DemoInterconnect_interface_axi_master_0_1}] -log ip_upgrade.log
export_ip_user_files -of_objects [get_ips {DemoInterconnect_interface_axi_master_0_0 DemoInterconnect_interface_axi_master_0_1}] -no_script -sync -force -quiet
generate_target all [get_files D:/Development/FPGA/InterNoC/InterNoC.srcs/sources_1/bd/DemoInterconnect/DemoInterconnect.bd]
catch { config_ip_cache -export [get_ips -all DemoInterconnect_interface_axi_master_0_0] }
catch { config_ip_cache -export [get_ips -all DemoInterconnect_interface_axi_master_0_1] }
catch { config_ip_cache -export [get_ips -all DemoInterconnect_axi_quad_spi_0_0] }
catch { config_ip_cache -export [get_ips -all DemoInterconnect_axi_quad_spi_0_1] }
catch { config_ip_cache -export [get_ips -all DemoInterconnect_axi_quad_spi_1_0] }
catch { config_ip_cache -export [get_ips -all DemoInterconnect_axi_quad_spi_2_0] }
catch { config_ip_cache -export [get_ips -all DemoInterconnect_auto_pc_0] }
export_ip_user_files -of_objects [get_files D:/Development/FPGA/InterNoC/InterNoC.srcs/sources_1/bd/DemoInterconnect/DemoInterconnect.bd] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] D:/Development/FPGA/InterNoC/InterNoC.srcs/sources_1/bd/DemoInterconnect/DemoInterconnect.bd]
launch_runs -jobs 3 {DemoInterconnect_axi_quad_spi_0_0_synth_1 DemoInterconnect_axi_quad_spi_0_1_synth_1 DemoInterconnect_axi_quad_spi_1_0_synth_1 DemoInterconnect_axi_quad_spi_2_0_synth_1 DemoInterconnect_interface_axi_master_0_0_synth_1 DemoInterconnect_interface_axi_master_0_1_synth_1}
export_simulation -of_objects [get_files D:/Development/FPGA/InterNoC/InterNoC.srcs/sources_1/bd/DemoInterconnect/DemoInterconnect.bd] -directory D:/Development/FPGA/InterNoC/InterNoC.ip_user_files/sim_scripts -ip_user_files_dir D:/Development/FPGA/InterNoC/InterNoC.ip_user_files -ipstatic_source_dir D:/Development/FPGA/InterNoC/InterNoC.ip_user_files/ipstatic -lib_map_path [list {modelsim=D:/Development/FPGA/InterNoC/InterNoC.cache/compile_simlib/modelsim} {questa=D:/Development/FPGA/InterNoC/InterNoC.cache/compile_simlib/questa} {riviera=D:/Development/FPGA/InterNoC/InterNoC.cache/compile_simlib/riviera} {activehdl=D:/Development/FPGA/InterNoC/InterNoC.cache/compile_simlib/activehdl}] -use_ip_compiled_libs -force -quiet
report_ip_status -name ip_status
relaunch_sim
restart
run 100 ns
restart
save_wave_config {D:/Development/FPGA/InterNoC/DemoInterconnect_TestBench_behav.wcfg}
relaunch_sim
restart
run 100 ns
run 100 ns
run 100 ns
run 100 ns
restart
relaunch_sim
open_bd_design {D:/Development/FPGA/InterNoC/InterNoC.srcs/sources_1/bd/DemoInterconnect/DemoInterconnect.bd}
update_ip_catalog -rebuild -scan_changes
report_ip_status -name ip_status
upgrade_ip [get_ips {DemoInterconnect_interface_axi_master_0_0 DemoInterconnect_interface_axi_master_0_1}] -log ip_upgrade.log
export_ip_user_files -of_objects [get_ips {DemoInterconnect_interface_axi_master_0_0 DemoInterconnect_interface_axi_master_0_1}] -no_script -sync -force -quiet
report_ip_status -name ip_status
relaunch_sim
relaunch_sim
relaunch_sim
relaunch_sim
close_sim