Skip to content

gubbriaco/FPGA-VHDL-Wallace-multiplier

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

30 Commits
 
 
 
 
 
 
 
 
 
 
 
 

Repository files navigation

Design and Analysis of an FPGA-based Wallace Multiplier


Project for the Bachelor's Degree thesis work in Computer Engineering: Design and analysis of an 8- and 16-bit Wallace multiplier. The hardware description was created with the help of the hardware description language VHDL and the Vivado Design Suite. Furthermore, a comparison was made with the traditional multiplier in terms of delay, resource occupation and power dissipation.

🗒️Thesis in .docx format: tesi.docx
🗒️Presentation in .ppt format: presentazione.ppt