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2018 02_Report
- A new MiSoC SPI core has been written that resolves several design issues in the old SPI core. It has simpler clock divider programming and usage, better defined output signal buffering and registering, and a programming interface that is much easier to use, especially in the case of compound SPI transactions that consist of multiple transfers. All in-tree ARTIQ drivers have been ported. The out-of-tree PDQ SPI coredevice driver was ported as well.
- Flashing, gateware, and firmware support has been added to Sayma to support loading the RTM FPGA bitstream from AMC flash during boot. This will replace the loading of the RTM FPGA bitstream over JTAG. Testing and debugging is ongoing.
- The bitstream loading during device boot in Kasli and Sayma has been accelerated by more than an order of magnitude.
Multiple different Kasli gateware variants are in use in various laboratories. Kasli/v1.1 has been manufactured and has seen preliminary testing.
We have continued to develop tooling for the I2C tree on Kasli and the attached EEMs bypassing the FPGA. This enables easy EEM EEPROM commissioning and debugging of hardware on the I2C bus. A layout for the Sinara EEPROM data has been outlined.
We have also implemented commissioning of the FT4232H EEPROM that defines the Kasli USB interface. This permits vendors to embed serial numbers and enables global identification of Kaslis.
Revision v1.1 of both Urukul variants has been manufactured and Urukul-AD9910/v1.1 has been tested successfully with Kasli and ARTIQ. We expect more than 30 Urukul boards to be in use in various laboratories soon.
We have released a new Urukul CPLD version implementing automatic latching of the shifted attenuator register settings on completion of the transfer and automatic loading of the status/configuration register at the beginning/end of a SPI transaction.
A new CPLD code pre-release targeting the changes in Urukul/v1.1 has been published.
The legacy 8 channel SPI ADC has received a complete ARTIQ coredevice driver interface. The driver was used to confirm specifications, and functionality of the design approach and is the basis for the upcoming Sampler driver. Novogorny is a legacy design and is expected to be outperformed and superseded by Sampler.