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HPC node architectures are trending toward large numbers of cores/CPUs, as well as accelerators such as GPUs. To make better use of shared resources within a node and to program accelerators, users have turned to hybrid programming that combines MPI with a node-level and data parallel programming models. The goal of this working group is to improve the programmability and performance of MPI+X usage models

Goals

Investigate support for MPI communication involving accelerators

• Hybrid programming of MPI + [CUDA, HIP, DPC++, ...]
• Host-initiated communication with accelerator memory
• Host-setup with accelerator triggering
• Host-setup, enqueued on a stream or queue
• Accelerator-initiated communication

Investigate improved compatibility/efficiency for multithreaded MPI communication

• MPI + [Pthreads, OpenMP, C/C++ threading, TBB, ...]

Chairs

• James Dinan -- jdinan (at) nvidia (dot) com

Mailing List

mpiwg-hybridpm (at) lists (dot) mpi-forum (dot) org -- Subscribe

Meeting Information

The HACC WG is currently sharing a meeting time with the Persistence WG.

Wednesdays, 10:00 AM - 11:00 AM ET

Meeting details and recordings are available here.

Active Topics

1. Continuations proposal #6
2. Clarification of thread ordering rules #117 (MPI 4.1)
3. Integration with accelerator programming models:
   1. Accelerator info keys #3 #714 (MPI 4.1)
   2. Accelerator Synchronous MPI Operations #11
   3. Accelerator bindings for partitioned communication #4
   4. Partitioned communication buffer preparation (shared with Persistence WG) #264
4. Asynchronous operations #585

2023 Meeting Schedule

• 4/26 -- Joseph Schuchart - Continuations
• 5/3 -- MPI Forum (No meeting)
• 5/10 -- Open
• 5/17 -- Rohit Zambre - Memory allocation kinds side document
• 5/24 -- ISC (No meeting)
• 5/31 -- Quincey Koziol - Truly async MPI operations
• 6/7 -- Open
• 6/14 -- Open
• 6/21 -- Open
• 6/28 -- Open
• 7/5 -- Open
• 7/12 -- Open
• 7/19 -- Open
• 7/26 -- Open