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Added a condition so that new Zfinx CSR only present when COREV_PULP = 1
Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr>
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Are we sure this is correct at line 1709:
(FPU = 0 | (FPU = 1 & ZFINX = 1))
Why would the zfinx CSR register exist when the FPU is not present, but not exist when the FPU is present but without ZFINX???
This register exists to tell software that uses the FPU whether it has ZFINX or not, so would only be checked if FPU=1.
(FPU=1 && ZFINX=1) appears to be the expression for the value of bit 0 in the register, not for whether the register is present.
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Hi @jstraus59
Here is a summary of what sees the software when looking at MISA.F which is the only information it can have using RISC-V defined CSRs (remember that software does not have access to RTL parameter values):
So from software point of view you need to discriminate when MISA.F = 0.
Without new Zfinx CSR implemented in CV32E40Pv2, there is no way to discriminate (!FPU & !ZFINX) and (FPU & ZFINX).
So for SW, first read MISA.F:
If 1 then ok F standard extension.
If 0 look at Zfinx CSR.
If 1 then Zfinx standard extension.
If 0 then no Floating Point support ...
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Thanks for the explanation. I had not realized misa.F == 0 when Zfinx is 1.
Another way to think about it is
The zfinx CSR is NOT implemented when FPU is implemented but Zfinx is not, as misa.F == 1 indicates that the FPRs are used by the FPU