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Error in Analysis and Synthesis in Quartus #943
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This RTL is correctly simulated by all 3 Siemens, Cadence and Synopsys simulators. |
My design for now doesn't include the fpu. I have simulated it and it works perfectly fine but gives errors in Quartus. I have set the project within the cv32e40p directory so it has access to all other directories and included all the files in the cv32e40p_manifest.flist in addition to my other soc files. It still gives me syntax errors. |
Hi @vidushiy25, can you provide the following:
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You can also remove cv32e40p_tracer_pkg from your qsf. |
I just tried the Analysis and Synthesis of the original untouched files from scratch by git cloning the repo into a different folder again and I get the same errors. I am using Quartus Prime Standard edition 23.1std.0. I made the project in the cv32e40p directory and added necessary files. Is there anything different that you did? I'm assuming I don't need the .sdc file until I start compilation. The target technology I used was the Cyclone IV EP4CE115F29C7. |
I used the cv32e40p_core as the top level entity as well. |
I made nothing special and didn't use any sdc. |
I did the exact same but our target technologies are different but I am still confused as to why it isn’t working. |
By looking on the net it seems standard edition is a quite old quartus code base and prime pro is essentially a re-write of nearly the entire code base. |
It is more talking about interface modports than packages import. I don't like that but move in every files the package import above the module name for the ones included in the module header and let me know if it resolves the pb on your side. |
This is not the same pb. |
So does this now have to do with difference of using Quartus Prime Pro vs Standard? |
Pro seems ok with original code. Try to move line 287 "genvar j;" in line 1132, just before generate
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Doesn't change anything.. |
Strange. |
I tried. Doesn't seem to work again. This would also mean modifying other files for this. I might consult the person supervising my project to consult other options for using other FPGAs. Thank you for your help! |
The FPGA implementation using Quartus Prime Standard doesn't work, but I can successfully make it work on Nexys4 (Artix-7) using Vivado. |
Siemens has a licensing strategy that allows users to control their licensing costs by restricting the HDL language constructs used in their RTL. For example, ModelSim is a low-cost HDL simulator that does not compile the full IEEE 1800-2017 LRM. At the OpenHW Group we deliberately exploit the advanced capabilities of languages and tools and that often means low-cost tools cannot support our IP. In the case of Quartus Prime Standard it is probably a good idea for us to explicitly mention this. I have created Issue #948 to track this. Thanks for working with us on this IP @vidushiy25! |
Hi, I'm trying to synthesise the core and its soc design on an Altera FPGA. But during the Analysis and Synthesis, it's giving me syntax errors in various source code files like the id_stage.sv, ex_stage.sv. The issue seems to be mostly coming from files which are importing packages and in some the syntax errors are deep within the source files like a variable being outside the scope. I have prioritised packages first in the list but it didn't make any difference.
I included all packages and files for the core in the same directory for Quartus synthesis.
Please advice.
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