Issue openhwgroup#813 correction.

Signed-off-by: Pascal Gouedo <pascal.gouedo@dolphin.fr>
pascalgouedo · May 31, 2023 · f2a1997 · f2a1997
1 parent cdee092
commit f2a1997
Showing 1 changed file with 15 additions and 0 deletions.
diff --git a/docs/source/instruction_set_extensions.rst b/docs/source/instruction_set_extensions.rst
@@ -1331,14 +1331,29 @@ SIMD ALU operations
   | **cv.srl[.sc,.sci]{.h,.b} rD, rs1, [rs2, Imm6]**           | rD[i] = rs1[i] >> op2[i]                                         |
   |                                                            |                                                                  |
   |                                                            | Note: Immediate is zero-extended, shift is logical.              |
+  |                                                            |                                                                  |
+  |                                                            | Only Imm6[3:0] and rs2[3:0] are used for .h instruction and      |
+  |                                                            | Imm6[2:0] and rs2[2:0] for .b instruction.                       |
+  |                                                            |                                                                  |
+  |                                                            | Other bits are not used and must be set to 0.                    |
   +------------------------------------------------------------+------------------------------------------------------------------+
   | **cv.sra[.sc,.sci]{.h,.b} rD, rs1, [rs2, Imm6]**           | rD[i] = rs1[i] >>> op2[i]                                        |
   |                                                            |                                                                  |
   |                                                            | Note: Immediate is zero-extended, shift is arithmetic.           |
+  |                                                            |                                                                  |
+  |                                                            | Only Imm6[3:0] and rs2[3:0] are used for .h instruction and      |
+  |                                                            | Imm6[2:0] and rs2[2:0] for .b instruction.                       |
+  |                                                            |                                                                  |
+  |                                                            | Other bits are not used and must be set to 0.                    |
   +------------------------------------------------------------+------------------------------------------------------------------+
   | **cv.sll[.sc,.sci]{.h,.b} rD, rs1, [rs2, Imm6]**           | rD[i] = rs1[i] << op2[i]                                         |
   |                                                            |                                                                  |
   |                                                            | Note: Immediate is zero-extended, shift is logical.              |
+  |                                                            |                                                                  |
+  |                                                            | Only Imm6[3:0] and rs2[3:0] are used for .h instruction and      |
+  |                                                            | Imm6[2:0] and rs2[2:0] for .b instruction.                       |
+  |                                                            |                                                                  |
+  |                                                            | Other bits are not used and must be set to 0.                    |
   +------------------------------------------------------------+------------------------------------------------------------------+
   | **cv.or[.sc,.sci]{.h,.b} rD, rs1, [rs2, Imm6]**            | rD[i] = rs1[i] \| op2[i]                                         |
   +------------------------------------------------------------+------------------------------------------------------------------+