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hw: Add SMP support to boot ROM #58

Merged
merged 7 commits into from
Aug 3, 2023
Merged

hw: Add SMP support to boot ROM #58

merged 7 commits into from
Aug 3, 2023

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niwis
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@niwis niwis commented Aug 2, 2023

Add SMP support in the bootrom. In particular,

  • pause all harts except 0 at the beginning of the bootrom,
  • let all harts jump to next boot stage after hart 0 finished bootrom,
  • park all harts except 0 at the beginning of crt0 for now (to be extended).

To facilitate this,

  • increase the number of scratch registers from 4 to 16 (e.g. for boot address synchronisation),
  • add a register containing the number of harts.

- Pause all harts except 0 at the beginning of the bootrom
- Let all harts jump to next boot stage after hart 0 finished bootrom
- Park all harts except 0 at the beginning of crt0 for now (to be extended)
- Increase number of scratch registers from 4 to 16 (e.g. for boot
address synchronisation)

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
paulsc96
paulsc96 previously approved these changes Aug 2, 2023
alex96295
alex96295 previously approved these changes Aug 3, 2023
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Fixes the MISP register layout

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
@paulsc96 paulsc96 changed the title bootrom: Support SMP hw: Add SMP support to boot ROM Aug 3, 2023
@paulsc96 paulsc96 merged commit 83f36ad into main Aug 3, 2023
18 checks passed
@paulsc96 paulsc96 deleted the nwistoff/smp branch August 3, 2023 20:36
MaistoV pushed a commit to MaistoV/cheshire_fork that referenced this pull request Aug 23, 2023
* bootrom: Support SMP

- Pause all harts except 0 at the beginning of the bootrom
- Let all harts jump to next boot stage after hart 0 finished bootrom
- Park all harts except 0 at the beginning of crt0 for now (to be extended)
- Increase number of scratch registers from 4 to 16 (e.g. for boot
address synchronisation)

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

* bootrom: Parametrise number of harts via cheshire_regs

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

* bootrom: Load word unsigned

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

* bootrom: Fix smp_resume jump target

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

* ci: Bump cheshire-nonfree

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

* clint: Bump v0.2.0

Fixes the MISP register layout

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

* clint.h: Update

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

---------

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
mattsini1 pushed a commit that referenced this pull request Aug 30, 2023
* bootrom: Support SMP

- Pause all harts except 0 at the beginning of the bootrom
- Let all harts jump to next boot stage after hart 0 finished bootrom
- Park all harts except 0 at the beginning of crt0 for now (to be extended)
- Increase number of scratch registers from 4 to 16 (e.g. for boot
address synchronisation)

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

* bootrom: Parametrise number of harts via cheshire_regs

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

* bootrom: Load word unsigned

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

* bootrom: Fix smp_resume jump target

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

* ci: Bump cheshire-nonfree

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

* clint: Bump v0.2.0

Fixes the MISP register layout

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

* clint.h: Update

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

---------

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Aquaticfuller pushed a commit that referenced this pull request Jul 16, 2024
Decouple HW, SW and simulation build targets
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3 participants