这是WHU武汉大学2022-2023学年 计卓班 计算机组成与设计 RISC-V CPU 单周期设计,包括Modelsim仿真测试,vivado下FPGA(NEXYS A7)测试。
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Updated
Jul 5, 2024 - Verilog
这是WHU武汉大学2022-2023学年 计卓班 计算机组成与设计 RISC-V CPU 单周期设计,包括Modelsim仿真测试,vivado下FPGA(NEXYS A7)测试。
RISC-V is an open-source instruction set architecture (ISA), enabling the implementation of central processing units (CPUs) or system-on-a-chip (SoC) designs without licensing fees. This makes it highly favored among FPGA enthusiasts for softcore processor implementations.
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