yosys
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Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
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Jan 30, 2023 - VHDL
Trying to verify Verilog/VHDL designs with formal methods and tools
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Mar 7, 2024 - VHDL
VHDL examples targeting the ICE40-HX8K development board using iceStorm + GHDL
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Jul 24, 2023 - VHDL
Open-Source VHDL Synthesis for Alhambra II FPGA Board
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Jun 30, 2022 - VHDL
Time domain to logarithmic frequency domain converter, as the polyphase FFT do for the linear.
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Oct 7, 2024 - VHDL
Design a Goertzel filter
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Oct 23, 2023 - VHDL
Fun project to produce (only) pulses as the MultiSignalGene do, with analogue circuits and FPGA or 74HC logic circuits.
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Oct 6, 2024 - VHDL
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