Merge pull request #136 from dmitrygx/topic/uct/ib_inline_int3

UCT/IB: Set correct CQE scatter value on DEVX and fix TX_INLINE_RESP=0 behavior
yosefe · Apr 20, 2021 · b09bfa1 · b09bfa1
2 parents cbb5c9d + 3abddaf
commit b09bfa1
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Showing 3 changed files with 4 additions and 3 deletions.
diff --git a/src/uct/ib/base/ib_iface.c b/src/uct/ib/base/ib_iface.c
@@ -1094,7 +1094,7 @@ UCS_CLASS_INIT_FUNC(uct_ib_iface_t, uct_ib_iface_ops_t *ops, uct_md_h md,
         goto err_destroy_comp_channel;
     }
 
-    inl = config->rx.inl;
+    inl = config->tx.inl_resp;
     status = uct_ib_iface_create_cq(self, init_attr->tx_cq_len, &inl,
                                     preferred_cpu, init_attr->flags,
                                     &self->cq[UCT_IB_DIR_TX]);

diff --git a/src/uct/ib/mlx5/dv/ib_mlx5_dv.c b/src/uct/ib/mlx5/dv/ib_mlx5_dv.c
@@ -127,7 +127,8 @@ ucs_status_t uct_ib_mlx5_devx_create_qp(uct_ib_iface_t *iface,
     UCT_IB_MLX5DV_SET(qpc, qpc, cqn_rcv, dvrcq.cqn);
     UCT_IB_MLX5DV_SET(qpc, qpc, log_sq_size, ucs_ilog2_or0(max_tx));
     UCT_IB_MLX5DV_SET(qpc, qpc, log_rq_size, ucs_ilog2_or0(max_rx));
-    UCT_IB_MLX5DV_SET(qpc, qpc, cs_req, UCT_IB_MLX5_QPC_CS_REQ_UP_TO_64B);
+    UCT_IB_MLX5DV_SET(qpc, qpc, cs_req,
+                      uct_ib_mlx5_qpc_cs_req(attr->max_inl_recv));
     UCT_IB_MLX5DV_SET(qpc, qpc, cs_res,
                       uct_ib_mlx5_qpc_cs_res(attr->max_inl_resp));
     UCT_IB_MLX5DV_SET64(qpc, qpc, dbr_addr, qp->devx.dbrec->offset);

diff --git a/src/uct/ib/mlx5/ib_mlx5.c b/src/uct/ib/mlx5/ib_mlx5.c
@@ -79,7 +79,7 @@ ucs_status_t uct_ib_mlx5_create_cq(struct ibv_context *context, int cqe,
     }
 
     *cq_p = cq;
-    *inl  = dv_attr.cqe_size / 2;
+    *inl  = (*inl > 0) ? (dv_attr.cqe_size / 2) : 0;
     return UCS_OK;
 #else
     return uct_ib_verbs_create_cq(context, cqe, channel, comp_vector,