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Merge pull request #14379 from OpenNuvoton/nvt_high_res_pwm
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Nuvoton: Enlarge NuMaker PWM duty cycle range
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0xc0170 authored Mar 11, 2021
2 parents dd7ca06 + 5b693ff commit 3061725
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Showing 18 changed files with 45 additions and 45 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -475,7 +475,7 @@ uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u3
uint32_t PWM_ConfigOutputChannel2(PWM_T *epwm,
uint32_t u32ChannelNum,
uint32_t u32Frequency,
uint32_t u32DutyCycle,
uint32_t u32HighDutyCycle,
uint32_t u32Frequency2);
void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
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Original file line number Diff line number Diff line change
Expand Up @@ -145,7 +145,7 @@ uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u
*/
uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
{
return PWM_ConfigOutputChannel2(pwm, u32ChannelNum, u32Frequency, u32DutyCycle, 1);
return PWM_ConfigOutputChannel2(pwm, u32ChannelNum, u32Frequency, u32DutyCycle*100, 1);
}

/**
Expand All @@ -155,13 +155,13 @@ uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u3
* - PWM1 : PWM Group 1
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
* @param[in] u32Frequency Target generator frequency = u32Frequency / u32Frequency2
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
* @param[in] u32HighDutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 10000. 1000 means 10%, 2000 means 20%...
* @param[in] u32Frequency2 Target generator frequency = u32Frequency / u32Frequency2
* @return Nearest frequency clock in nano second
* @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure PWM frequency may affect
* existing frequency of other channel.
*/
uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle, uint32_t u32Frequency2)
uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32HighDutyCycle, uint32_t u32Frequency2)
{
uint32_t u32Src;
uint32_t u32PWMClockSrc;
Expand Down Expand Up @@ -219,12 +219,12 @@ uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u
u16CNR -= 1UL;
PWM_SET_CNR(pwm, u32ChannelNum, u16CNR);

if (u32DutyCycle)
if (u32HighDutyCycle)
{
if (u32DutyCycle >= 100UL)
if (u32HighDutyCycle >= 10000UL)
PWM_SET_CMR(pwm, u32ChannelNum, u16CNR);
else
PWM_SET_CMR(pwm, u32ChannelNum, u32DutyCycle * (u16CNR + 1UL) / 100UL);
PWM_SET_CMR(pwm, u32ChannelNum, u32HighDutyCycle * (u16CNR + 1UL) / 10000UL);

(pwm)->WGCTL0 &= ~((PWM_WGCTL0_PRDPCTL0_Msk | PWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1UL));
(pwm)->WGCTL0 |= (PWM_OUTPUT_LOW << ((u32ChannelNum << 1UL) + PWM_WGCTL0_PRDPCTL0_Pos));
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4 changes: 2 additions & 2 deletions targets/TARGET_NUVOTON/TARGET_M251/pwmout_api.c
Original file line number Diff line number Diff line change
Expand Up @@ -195,10 +195,10 @@ static void pwmout_config(pwmout_t *obj, int start)

// NOTE: Support period < 1s
// NOTE: ARM mbed CI test fails due to first PWM pulse error. Workaround by:
// 1. Inverse duty cycle (100 - duty)
// 1. Inverse duty cycle (10000 - duty)
// 2. Inverse PWM output polarity
// This trick is here to pass ARM mbed CI test. First PWM pulse error still remains.
PWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 100 - obj->pulsewidth_us * 100 / obj->period_us, obj->period_us);
PWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 10000 - obj->pulsewidth_us * 10000 / obj->period_us, obj->period_us);
pwm_base->POLCTL |= 1 << (PWM_POLCTL_PINV0_Pos + chn);

if (start) {
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Original file line number Diff line number Diff line change
Expand Up @@ -126,7 +126,7 @@ uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_
*/
uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
{
return EPWM_ConfigOutputChannel2(epwm, u32ChannelNum, u32Frequency, u32DutyCycle, 1);
return EPWM_ConfigOutputChannel2(epwm, u32ChannelNum, u32Frequency, u32DutyCycle*100, 1);
}

/**
Expand All @@ -136,15 +136,15 @@ uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t
* - EPWM1 : EPWM Group 1
* @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
* @param[in] u32Frequency Target generator frequency
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
* @param[in] u32HighDutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 10000. 1000 means 10%, 2000 means 20%...
* @param[in] u32Frequency2 Target generator frequency = u32Frequency / u32Frequency2
* @return Nearest frequency clock in nano second
* @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure EPWM frequency may affect
* existing frequency of other channel.
* @note This function is used for initial stage.
* To change duty cycle later, it should get the configured period value and calculate the new comparator value.
*/
uint32_t EPWM_ConfigOutputChannel2(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle, uint32_t u32Frequency2)
uint32_t EPWM_ConfigOutputChannel2(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32HighDutyCycle, uint32_t u32Frequency2)
{
uint32_t u32PWMClockSrc;
uint32_t i;
Expand Down Expand Up @@ -183,7 +183,7 @@ uint32_t EPWM_ConfigOutputChannel2(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_

u32CNR = u32CNR - 1U;
EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR);
EPWM_SET_CMR(epwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1UL) / 100UL);
EPWM_SET_CMR(epwm, u32ChannelNum, u32HighDutyCycle * (u32CNR + 1UL) / 10000UL);

(epwm)->WGCTL0 = ((epwm)->WGCTL0 & ~((EPWM_WGCTL0_PRDPCTL0_Msk | EPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1))) | \
(EPWM_OUTPUT_HIGH << (u32ChannelNum << 1UL << EPWM_WGCTL0_ZPCTL0_Pos));
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -566,7 +566,7 @@ uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t
uint32_t EPWM_ConfigOutputChannel2(EPWM_T *epwm,
uint32_t u32ChannelNum,
uint32_t u32Frequency,
uint32_t u32DutyCycle,
uint32_t u32HighDutyCycle,
uint32_t u32Frequency2);
void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask);
void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask);
Expand Down
4 changes: 2 additions & 2 deletions targets/TARGET_NUVOTON/TARGET_M261/pwmout_api.c
Original file line number Diff line number Diff line change
Expand Up @@ -195,10 +195,10 @@ static void pwmout_config(pwmout_t *obj, int start)

// NOTE: Support period < 1s
// NOTE: ARM mbed CI test fails due to first PWM pulse error. Workaround by:
// 1. Inverse duty cycle (100 - duty)
// 1. Inverse duty cycle (10000 - duty)
// 2. Inverse PWM output polarity
// This trick is here to pass ARM mbed CI test. First PWM pulse error still remains.
EPWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 100 - obj->pulsewidth_us * 100 / obj->period_us, obj->period_us);
EPWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 10000 - obj->pulsewidth_us * 10000 / obj->period_us, obj->period_us);
pwm_base->POLCTL |= 1 << (EPWM_POLCTL_PINV0_Pos + chn);

if (start) {
Expand Down
10 changes: 5 additions & 5 deletions targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_pwm.c
Original file line number Diff line number Diff line change
Expand Up @@ -107,15 +107,15 @@ uint32_t PWM_ConfigOutputChannel (PWM_T *pwm,
uint32_t u32Frequency,
uint32_t u32DutyCycle)
{
return PWM_ConfigOutputChannel2(pwm, u32ChannelNum, u32Frequency, u32DutyCycle, 1);
return PWM_ConfigOutputChannel2(pwm, u32ChannelNum, u32Frequency, u32DutyCycle*100, 1);
}

/**
* @brief This function config PWM generator and get the nearest frequency in edge aligned auto-reload mode
* @param[in] pwm The base address of PWM module
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
* @param[in] u32Frequency Target generator frequency = u32Frequency / u32Frequency2
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
* @param[in] u32HighDutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 10000. 1000 means 10%, 2000 means 20%...
* @param[in] u32Frequency2 Target generator frequency = u32Frequency / u32Frequency2
* @return Nearest frequency clock in nano second
* @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
Expand All @@ -124,7 +124,7 @@ uint32_t PWM_ConfigOutputChannel (PWM_T *pwm,
uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm,
uint32_t u32ChannelNum,
uint32_t u32Frequency,
uint32_t u32DutyCycle,
uint32_t u32HighDutyCycle,
uint32_t u32Frequency2)
{
uint32_t u32Src;
Expand Down Expand Up @@ -176,9 +176,9 @@ uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm,
(pwm)->CTL1 &= ~(PWM_CTL1_CNTMODE0_Msk << u32ChannelNum);

PWM_SET_CNR(pwm, u32ChannelNum, --u16CNR);
if(u32DutyCycle)
if(u32HighDutyCycle)
{
PWM_SET_CMR(pwm, u32ChannelNum, u32DutyCycle * (u16CNR + 1) / 100 - 1);
PWM_SET_CMR(pwm, u32ChannelNum, u32HighDutyCycle * (u16CNR + 1) / 10000 - 1);
(pwm)->WGCTL0 &= ~((PWM_WGCTL0_PRDPCTL0_Msk | PWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum * 2));
(pwm)->WGCTL0 |= (PWM_OUTPUT_LOW << (u32ChannelNum * 2 + PWM_WGCTL0_PRDPCTL0_Pos));
(pwm)->WGCTL1 &= ~((PWM_WGCTL1_CMPDCTL0_Msk | PWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum * 2));
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -476,7 +476,7 @@ uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u3
uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm,
uint32_t u32ChannelNum,
uint32_t u32Frequency,
uint32_t u32DutyCycle,
uint32_t u32HighDutyCycle,
uint32_t u32Frequency2);
void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
Expand Down
2 changes: 1 addition & 1 deletion targets/TARGET_NUVOTON/TARGET_M451/pwmout_api.c
Original file line number Diff line number Diff line change
Expand Up @@ -195,7 +195,7 @@ static void pwmout_config(pwmout_t *obj)
uint32_t chn = NU_MODSUBINDEX(obj->pwm);
// NOTE: Support period < 1s
//PWM_ConfigOutputChannel(pwm_base, chn, 1000 * 1000 / obj->period_us, obj->pulsewidth_us * 100 / obj->period_us);
PWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, obj->pulsewidth_us * 100 / obj->period_us, obj->period_us);
PWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, obj->pulsewidth_us * 10000 / obj->period_us, obj->period_us);
}

const PinMap *pwmout_pinmap()
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -541,7 +541,7 @@ uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t
uint32_t EPWM_ConfigOutputChannel2(EPWM_T *epwm,
uint32_t u32ChannelNum,
uint32_t u32Frequency,
uint32_t u32DutyCycle,
uint32_t u32HighDutyCycle,
uint32_t u32Frequency2);
void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask);
void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask);
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -135,7 +135,7 @@ uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_
*/
uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
{
return EPWM_ConfigOutputChannel2(epwm, u32ChannelNum, u32Frequency, u32DutyCycle, 1);
return EPWM_ConfigOutputChannel2(epwm, u32ChannelNum, u32Frequency, u32DutyCycle*100, 1);
}

/**
Expand All @@ -145,15 +145,15 @@ uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t
* - EPWM1 : EPWM Group 1
* @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
* @param[in] u32Frequency Target generator frequency / u32Frequency2
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
* @param[in] u32HighDutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 10000. 1000 means 10%, 2000 means 20%...
* @param[in] u32Frequency2 Target generator frequency = u32Frequency / u32Frequency2
* @return Nearest frequency clock in nano second
* @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure EPWM frequency may affect
* existing frequency of other channel.
* @note This function is used for initial stage.
* To change duty cycle later, it should get the configured period value and calculate the new comparator value.
*/
uint32_t EPWM_ConfigOutputChannel2(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle, uint32_t u32Frequency2)
uint32_t EPWM_ConfigOutputChannel2(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32HighDutyCycle, uint32_t u32Frequency2)
{
uint32_t u32Src;
uint32_t u32EPWMClockSrc;
Expand Down Expand Up @@ -211,7 +211,7 @@ uint32_t EPWM_ConfigOutputChannel2(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_

u32CNR -= 1U;
EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR);
EPWM_SET_CMR(epwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1U) / 100U);
EPWM_SET_CMR(epwm, u32ChannelNum, u32HighDutyCycle * (u32CNR + 1U) / 10000U);

(epwm)->WGCTL0 = ((epwm)->WGCTL0 & ~(((1UL << EPWM_WGCTL0_PRDPCTL0_Pos) | (1UL << EPWM_WGCTL0_ZPCTL0_Pos)) << (u32ChannelNum << 1U))) | \
((uint32_t)EPWM_OUTPUT_HIGH << ((u32ChannelNum << 1U) + (uint32_t)EPWM_WGCTL0_ZPCTL0_Pos));
Expand Down
4 changes: 2 additions & 2 deletions targets/TARGET_NUVOTON/TARGET_M480/pwmout_api.c
Original file line number Diff line number Diff line change
Expand Up @@ -198,10 +198,10 @@ static void pwmout_config(pwmout_t *obj, int start)

// NOTE: Support period < 1s
// NOTE: ARM mbed CI test fails due to first PWM pulse error. Workaround by:
// 1. Inverse duty cycle (100 - duty)
// 1. Inverse duty cycle (10000 - duty)
// 2. Inverse PWM output polarity
// This trick is here to pass ARM mbed CI test. First PWM pulse error still remains.
EPWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 100 - obj->pulsewidth_us * 100 / obj->period_us, obj->period_us);
EPWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 10000 - obj->pulsewidth_us * 10000 / obj->period_us, obj->period_us);
pwm_base->POLCTL |= 1 << (EPWM_POLCTL_PINV0_Pos + chn);

if (start) {
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -38,23 +38,23 @@ uint32_t PWM_ConfigOutputChannel (PWM_T *pwm,
uint32_t u32Frequency,
uint32_t u32DutyCycle)
{
return PWM_ConfigOutputChannel2(pwm, u32ChannelNum, u32Frequency, u32DutyCycle, 1);
return PWM_ConfigOutputChannel2(pwm, u32ChannelNum, u32Frequency, u32DutyCycle*100, 1);
}

/**
* @brief This function config PWM generator and get the nearest frequency in edge aligned auto-reload mode
* @param[in] pwm The base address of PWM module
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
* @param[in] u32Frequency Target generator frequency
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
* @param[in] u32HighDutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 10000. 1000 means 10%, 2000 means 20%...
* @return Nearest frequency clock in nano second
* @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
* existing frequency of other channel.
*/
uint32_t PWM_ConfigOutputChannel2 (PWM_T *pwm,
uint32_t u32ChannelNum,
uint32_t u32Frequency,
uint32_t u32DutyCycle,
uint32_t u32HighDutyCycle,
uint32_t u32Frequency2)
{
uint32_t i;
Expand Down Expand Up @@ -132,11 +132,11 @@ uint32_t PWM_ConfigOutputChannel2 (PWM_T *pwm,
pwm->CLKSEL = (pwm->CLKSEL & ~(PWM_CLKSEL_CLKSEL0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum));
pwm->CTL |= (PWM_CTL_CH0MOD_Msk << (u32ChannelNum * 8));
while((pwm->INTSTS & (PWM_INTSTS_DUTY0SYNC_Msk << u32ChannelNum)) == (PWM_INTSTS_DUTY0SYNC_Msk << u32ChannelNum));
if(u32DutyCycle == 0)
if(u32HighDutyCycle == 0)
*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CM_Msk;
else {
*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CM_Msk;
*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= ((u32DutyCycle * (u16CNR + 1) / 100 - 1) << PWM_DUTY_CM_Pos);
*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= ((u32HighDutyCycle * (u16CNR + 1) / 10000 - 1) << PWM_DUTY_CM_Pos);
}
*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) &= ~PWM_DUTY_CN_Msk;
*(__IO uint32_t *) (&pwm->DUTY0 + 3 * u32ChannelNum) |= u16CNR;
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -168,7 +168,7 @@ uint32_t PWM_ConfigOutputChannel(PWM_T *pwm,
uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm,
uint32_t u32ChannelNum,
uint32_t u32Frequency,
uint32_t u32DutyCycle,
uint32_t u32HighDutyCycle,
uint32_t u32Frequency2);
uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
uint32_t u32ChannelNum,
Expand Down
4 changes: 2 additions & 2 deletions targets/TARGET_NUVOTON/TARGET_NANO100/pwmout_api.c
Original file line number Diff line number Diff line change
Expand Up @@ -198,10 +198,10 @@ static void pwmout_config(pwmout_t *obj)
uint32_t chn = NU_MODSUBINDEX(obj->pwm);
// NOTE: Support period < 1s
// NOTE: ARM mbed CI test fails due to first PWM pulse error. Workaround by:
// 1. Inverse duty cycle (100 - duty)
// 1. Inverse duty cycle (10000 - duty)
// 2. Inverse PWM output polarity
// This trick is here to pass ARM mbed CI test. First PWM pulse error still remains.
PWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 100 - (obj->pulsewidth_us * 100 / obj->period_us), obj->period_us);
PWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 10000 - (obj->pulsewidth_us * 10000 / obj->period_us), obj->period_us);
}

const PinMap *pwmout_pinmap()
Expand Down
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