这是WHU武汉大学2022-2023学年 计卓班 计算机组成与设计 RISC-V CPU 单周期设计,包括Modelsim仿真测试,vivado下FPGA(NEXYS A7)测试。
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Updated
Jul 5, 2024 - Verilog
这是WHU武汉大学2022-2023学年 计卓班 计算机组成与设计 RISC-V CPU 单周期设计,包括Modelsim仿真测试,vivado下FPGA(NEXYS A7)测试。
🎓💻University of Tehran Computer Architecture Course Projects - Spring 2021
Implementation of Computer Architecture Consepts, Including Multiplier , Control Module, Verilog Elevator, Single cycle processor and mips pipeline with new forwarding unit.
This repository consists of Load, Store and Read word data paths using a Single Cycle Core.
A single cycle CPU has been constructed in Verilog.
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