RISC-V-single-cycle-core-Logisim

Introduction

Logisim allows you to design and simulate digital circuits. It is intended as an educational tool, to help you learn how circuits work.

Design

RV32I signle cycle simulation on an open source software Logisim This repository is for RISC-V single cycle core. Team UIT has completed the whole implementation of a 32-Bit Single Cycle RISC-V Core on Logisim as well as on Chisel and developed the verilog file of it from the Chisel code. The core is being tested on FPGA now. To view the simmulation you have to install Logisim, an open source software as well as java run time enviourment.